From patchwork Fri Mar 31 06:18:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 13195250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76D49C77B60 for ; Fri, 31 Mar 2023 06:18:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230132AbjCaGSu (ORCPT ); Fri, 31 Mar 2023 02:18:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230047AbjCaGSn (ORCPT ); Fri, 31 Mar 2023 02:18:43 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 298CE3C20; Thu, 30 Mar 2023 23:18:43 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32V5jFmJ019985; Fri, 31 Mar 2023 06:18:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=f/vVrLbjYNoac+duJcW+BhpAcjKHzIiJxKtah+6l4rI=; b=h1WmfcZwx6w4y+H/Z2yORwDxY9r9vuQFT4aoo6tuCzQmssjdsQ1XGE8WFvtfiuhEPMue PdC9KvFWcsNrGB8Bk9S0A5lauxNSrV98l3/hyKjAbh9o/p2shmdNvVAq/YL3+7VP2TJl ZaSDbCB67EBezS/UAmWWhXH9O7m0ca5/smcpMjFLW18XUaVTUj2RaK5R1IZSEwKM9yqE zs/UIpkV1HFALLFnwk3Qsm95CHsQNsTidYMCVetfBPXIupLSybbmOAYXVbV43oZNgR+W Qw89jQNHWeAikQVCsxr0N/1QqCsByBVb37AOc1Xr2yOhWxgW440H3HRtaO7c7gK2sh8N cg== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pn934tjbd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 31 Mar 2023 06:18:36 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 32V6IWIS013904; Fri, 31 Mar 2023 06:18:33 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3pht1knm2n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 31 Mar 2023 06:18:33 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 32V6IWid013895; Fri, 31 Mar 2023 06:18:32 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.213.106.138]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 32V6IWLH013915; Fri, 31 Mar 2023 06:18:32 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 0746B4EED; Fri, 31 Mar 2023 11:48:32 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org, bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH v5 5/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP Date: Fri, 31 Mar 2023 11:48:22 +0530 Message-Id: <1680243502-23744-6-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1680243502-23744-1-git-send-email-quic_rohiagar@quicinc.com> References: <1680243502-23744-1-git-send-email-quic_rohiagar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: HAc_AtjRW_6fXFm_xABy5V8BVs6rAu6j X-Proofpoint-ORIG-GUID: HAc_AtjRW_6fXFm_xABy5V8BVs6rAu6j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-31_02,2023-03-30_04,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 mlxscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 mlxlogscore=685 clxscore=1015 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303310050 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable PCIe Endpoint controller on the SDX65 MTP board based on Qualcomm SDX65 platform. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 70720e6..96da625 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -245,6 +245,18 @@ status = "okay"; }; +&pcie_ep { + pinctrl-0 = <&pcie_ep_clkreq_default + &pcie_ep_perst_default + &pcie_ep_wake_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + &pcie_phy { vdda-phy-supply = <&vreg_l1b_1p2>; vdda-pll-supply = <&vreg_l4b_0p88>; @@ -277,6 +289,29 @@ status = "okay"; }; +&tlmm { + pcie_ep_clkreq_default: pcie-ep-clkreq-default-state { + pins = "gpio56"; + function = "pcie_clkreq"; + drive-strength = <2>; + bias-disable; + }; + + pcie_ep_perst_default: pcie-ep-perst-default-state { + pins = "gpio57"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + pcie_ep_wake_default: pcie-ep-wake-default-state { + pins = "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + &usb { status = "okay"; };