| Message ID | 1684325894-30252-2-git-send-email-quic_vnivarth@quicinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 6d6e57594957ee9131bc3802dfc8657ca6f78fee |
| Headers | show |
| Series | spi-geni-qcom: Add new interfaces and utilise them to do map/unmap in framework for SE DMA | expand |
Hi, On Wed, May 17, 2023 at 5:18 AM Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> wrote: > > The geni_se_xx_dma_prep() interfaces necessarily do DMA mapping before > initiating DMA transfers. This is not suitable for spi where framework > is expected to handle map/unmap. > > Expose new interfaces geni_se_xx_init_dma() which do only DMA transfer. > > Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> > --- > v1 -> v2: > - interfaces to take dma address as argument instead of its pointer > --- > drivers/soc/qcom/qcom-geni-se.c | 67 +++++++++++++++++++++++++++++----------- > include/linux/soc/qcom/geni-se.h | 4 +++ > 2 files changed, 53 insertions(+), 18 deletions(-) Mark and Bjorn will have to coordinate how they want to land this, since normally patch #1 would go through the Qualcomm tree and patch #2 through the SPI tree. In any case: Reviewed-by: Douglas Anderson <dianders@chromium.org>
On Wed, May 17, 2023 at 07:18:17AM -0700, Doug Anderson wrote: > On Wed, May 17, 2023 at 5:18 AM Vijaya Krishna Nivarthi > > The geni_se_xx_dma_prep() interfaces necessarily do DMA mapping before > > initiating DMA transfers. This is not suitable for spi where framework > > is expected to handle map/unmap. > Mark and Bjorn will have to coordinate how they want to land this, > since normally patch #1 would go through the Qualcomm tree and patch > #2 through the SPI tree. In any case: Bjorn?
On 17.05.2023 14:18, Vijaya Krishna Nivarthi wrote: > The geni_se_xx_dma_prep() interfaces necessarily do DMA mapping before > initiating DMA transfers. This is not suitable for spi where framework > is expected to handle map/unmap. > > Expose new interfaces geni_se_xx_init_dma() which do only DMA transfer. > > Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > v1 -> v2: > - interfaces to take dma address as argument instead of its pointer > --- > drivers/soc/qcom/qcom-geni-se.c | 67 +++++++++++++++++++++++++++++----------- > include/linux/soc/qcom/geni-se.h | 4 +++ > 2 files changed, 53 insertions(+), 18 deletions(-) > > diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c > index 795a2e1..dd50a25 100644 > --- a/drivers/soc/qcom/qcom-geni-se.c > +++ b/drivers/soc/qcom/qcom-geni-se.c > @@ -682,6 +682,30 @@ EXPORT_SYMBOL(geni_se_clk_freq_match); > #define GENI_SE_DMA_EOT_EN BIT(1) > #define GENI_SE_DMA_AHB_ERR_EN BIT(2) > #define GENI_SE_DMA_EOT_BUF BIT(0) > + > +/** > + * geni_se_tx_init_dma() - Initiate TX DMA transfer on the serial engine > + * @se: Pointer to the concerned serial engine. > + * @iova: Mapped DMA address. > + * @len: Length of the TX buffer. > + * > + * This function is used to initiate DMA TX transfer. > + */ > +void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len) > +{ > + u32 val; > + > + val = GENI_SE_DMA_DONE_EN; > + val |= GENI_SE_DMA_EOT_EN; > + val |= GENI_SE_DMA_AHB_ERR_EN; > + writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); > + writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_TX_PTR_L); > + writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_TX_PTR_H); > + writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); > + writel(len, se->base + SE_DMA_TX_LEN); > +} > +EXPORT_SYMBOL(geni_se_tx_init_dma); > + > /** > * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer > * @se: Pointer to the concerned serial engine. > @@ -697,7 +721,6 @@ int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, > dma_addr_t *iova) > { > struct geni_wrapper *wrapper = se->wrapper; > - u32 val; > > if (!wrapper) > return -EINVAL; > @@ -706,17 +729,34 @@ int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, > if (dma_mapping_error(wrapper->dev, *iova)) > return -EIO; > > + geni_se_tx_init_dma(se, *iova, len); > + return 0; > +} > +EXPORT_SYMBOL(geni_se_tx_dma_prep); > + > +/** > + * geni_se_rx_init_dma() - Initiate RX DMA transfer on the serial engine > + * @se: Pointer to the concerned serial engine. > + * @iova: Mapped DMA address. > + * @len: Length of the RX buffer. > + * > + * This function is used to initiate DMA RX transfer. > + */ > +void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len) > +{ > + u32 val; > + > val = GENI_SE_DMA_DONE_EN; > val |= GENI_SE_DMA_EOT_EN; > val |= GENI_SE_DMA_AHB_ERR_EN; > - writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); > - writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L); > - writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); > - writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); > - writel(len, se->base + SE_DMA_TX_LEN); > - return 0; > + writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); > + writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_RX_PTR_L); > + writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_RX_PTR_H); > + /* RX does not have EOT buffer type bit. So just reset RX_ATTR */ > + writel_relaxed(0, se->base + SE_DMA_RX_ATTR); > + writel(len, se->base + SE_DMA_RX_LEN); > } > -EXPORT_SYMBOL(geni_se_tx_dma_prep); > +EXPORT_SYMBOL(geni_se_rx_init_dma); > > /** > * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer > @@ -733,7 +773,6 @@ int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, > dma_addr_t *iova) > { > struct geni_wrapper *wrapper = se->wrapper; > - u32 val; > > if (!wrapper) > return -EINVAL; > @@ -742,15 +781,7 @@ int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, > if (dma_mapping_error(wrapper->dev, *iova)) > return -EIO; > > - val = GENI_SE_DMA_DONE_EN; > - val |= GENI_SE_DMA_EOT_EN; > - val |= GENI_SE_DMA_AHB_ERR_EN; > - writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); > - writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L); > - writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); > - /* RX does not have EOT buffer type bit. So just reset RX_ATTR */ > - writel_relaxed(0, se->base + SE_DMA_RX_ATTR); > - writel(len, se->base + SE_DMA_RX_LEN); > + geni_se_rx_init_dma(se, *iova, len); > return 0; > } > EXPORT_SYMBOL(geni_se_rx_dma_prep); > diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h > index c55a0bc..821a191 100644 > --- a/include/linux/soc/qcom/geni-se.h > +++ b/include/linux/soc/qcom/geni-se.h > @@ -490,9 +490,13 @@ int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, > unsigned int *index, unsigned long *res_freq, > bool exact); > > +void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len); > + > int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, > dma_addr_t *iova); > > +void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len); > + > int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, > dma_addr_t *iova); >
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 795a2e1..dd50a25 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -682,6 +682,30 @@ EXPORT_SYMBOL(geni_se_clk_freq_match); #define GENI_SE_DMA_EOT_EN BIT(1) #define GENI_SE_DMA_AHB_ERR_EN BIT(2) #define GENI_SE_DMA_EOT_BUF BIT(0) + +/** + * geni_se_tx_init_dma() - Initiate TX DMA transfer on the serial engine + * @se: Pointer to the concerned serial engine. + * @iova: Mapped DMA address. + * @len: Length of the TX buffer. + * + * This function is used to initiate DMA TX transfer. + */ +void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len) +{ + u32 val; + + val = GENI_SE_DMA_DONE_EN; + val |= GENI_SE_DMA_EOT_EN; + val |= GENI_SE_DMA_AHB_ERR_EN; + writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); + writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_TX_PTR_L); + writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_TX_PTR_H); + writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); + writel(len, se->base + SE_DMA_TX_LEN); +} +EXPORT_SYMBOL(geni_se_tx_init_dma); + /** * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer * @se: Pointer to the concerned serial engine. @@ -697,7 +721,6 @@ int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, dma_addr_t *iova) { struct geni_wrapper *wrapper = se->wrapper; - u32 val; if (!wrapper) return -EINVAL; @@ -706,17 +729,34 @@ int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, if (dma_mapping_error(wrapper->dev, *iova)) return -EIO; + geni_se_tx_init_dma(se, *iova, len); + return 0; +} +EXPORT_SYMBOL(geni_se_tx_dma_prep); + +/** + * geni_se_rx_init_dma() - Initiate RX DMA transfer on the serial engine + * @se: Pointer to the concerned serial engine. + * @iova: Mapped DMA address. + * @len: Length of the RX buffer. + * + * This function is used to initiate DMA RX transfer. + */ +void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len) +{ + u32 val; + val = GENI_SE_DMA_DONE_EN; val |= GENI_SE_DMA_EOT_EN; val |= GENI_SE_DMA_AHB_ERR_EN; - writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); - writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L); - writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); - writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); - writel(len, se->base + SE_DMA_TX_LEN); - return 0; + writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); + writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_RX_PTR_L); + writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_RX_PTR_H); + /* RX does not have EOT buffer type bit. So just reset RX_ATTR */ + writel_relaxed(0, se->base + SE_DMA_RX_ATTR); + writel(len, se->base + SE_DMA_RX_LEN); } -EXPORT_SYMBOL(geni_se_tx_dma_prep); +EXPORT_SYMBOL(geni_se_rx_init_dma); /** * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer @@ -733,7 +773,6 @@ int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, dma_addr_t *iova) { struct geni_wrapper *wrapper = se->wrapper; - u32 val; if (!wrapper) return -EINVAL; @@ -742,15 +781,7 @@ int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, if (dma_mapping_error(wrapper->dev, *iova)) return -EIO; - val = GENI_SE_DMA_DONE_EN; - val |= GENI_SE_DMA_EOT_EN; - val |= GENI_SE_DMA_AHB_ERR_EN; - writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); - writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L); - writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); - /* RX does not have EOT buffer type bit. So just reset RX_ATTR */ - writel_relaxed(0, se->base + SE_DMA_RX_ATTR); - writel(len, se->base + SE_DMA_RX_LEN); + geni_se_rx_init_dma(se, *iova, len); return 0; } EXPORT_SYMBOL(geni_se_rx_dma_prep); diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h index c55a0bc..821a191 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -490,9 +490,13 @@ int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, unsigned int *index, unsigned long *res_freq, bool exact); +void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len); + int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, dma_addr_t *iova); +void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len); + int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, dma_addr_t *iova);
The geni_se_xx_dma_prep() interfaces necessarily do DMA mapping before initiating DMA transfers. This is not suitable for spi where framework is expected to handle map/unmap. Expose new interfaces geni_se_xx_init_dma() which do only DMA transfer. Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> --- v1 -> v2: - interfaces to take dma address as argument instead of its pointer --- drivers/soc/qcom/qcom-geni-se.c | 67 +++++++++++++++++++++++++++++----------- include/linux/soc/qcom/geni-se.h | 4 +++ 2 files changed, 53 insertions(+), 18 deletions(-)