diff mbox series

[v3,1/3] arm64: dts: qcom: Add interconnect nodes for SDX75

Message ID 1696327472-21776-2-git-send-email-quic_rohiagar@quicinc.com (mailing list archive)
State Superseded
Headers show
Series Add devicetree support of Interconnects and USB for SDX75 | expand

Commit Message

Rohit Agarwal Oct. 3, 2023, 10:04 a.m. UTC 
Add interconnect nodes to support interconnects on SDX75.
Also parallely add the interconnect property for UART required
so that the bootup to shell does not break with interconnects
in place.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sdx75.dtsi | 52 +++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

Comments

Dmitry Baryshkov Oct. 3, 2023, 10:05 a.m. UTC | #1 
On Tue, 3 Oct 2023 at 13:04, Rohit Agarwal <quic_rohiagar@quicinc.com> wrote:
>
> Add interconnect nodes to support interconnects on SDX75.
> Also parallely add the interconnect property for UART required
> so that the bootup to shell does not break with interconnects
> in place.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sdx75.dtsi | 52 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 52 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
> index e180aa4..ac0b785 100644
> --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
> @@ -8,6 +8,8 @@
>
>  #include <dt-bindings/clock/qcom,rpmh.h>
>  #include <dt-bindings/clock/qcom,sdx75-gcc.h>
> +#include <dt-bindings/interconnect/qcom,icc.h>
> +#include <dt-bindings/interconnect/qcom,sdx75.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/power/qcom,rpmhpd.h>
>  #include <dt-bindings/power/qcom-rpmpd.h>
> @@ -197,6 +199,19 @@
>                 };
>         };
>
> +       clk_virt: interconnect-0 {
> +               compatible = "qcom,sdx75-clk-virt";
> +               #interconnect-cells = <2>;
> +               qcom,bcm-voters = <&apps_bcm_voter>;
> +               clocks = <&rpmhcc RPMH_QPIC_CLK>;
> +       };
> +
> +       mc_virt: interconnect-1 {
> +               compatible = "qcom,sdx75-mc-virt";
> +               #interconnect-cells = <2>;
> +               qcom,bcm-voters = <&apps_bcm_voter>;
> +       };

Interconnect comes after firmware, 'i' > 'f'.

> +
>         firmware {
>                 scm: scm {
>                         compatible = "qcom,scm-sdx75", "qcom,scm";
> @@ -434,6 +449,9 @@
>                         clock-names = "m-ahb",
>                                       "s-ahb";
>                         iommus = <&apps_smmu 0xe3 0x0>;
> +                       interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
> +                                        &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
> +                       interconnect-names = "qup-core";
>                         #address-cells = <2>;
>                         #size-cells = <2>;
>                         ranges;
> @@ -444,6 +462,12 @@
>                                 reg = <0x0 0x00984000 0x0 0x4000>;
>                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
>                                 clock-names = "se";
> +                               interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
> +                                                &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
> +                                               <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> +                                                &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
> +                               interconnect-names = "qup-core",
> +                                                    "qup-config";
>                                 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
>                                 pinctrl-0 = <&qupv3_se1_2uart_active>;
>                                 pinctrl-1 = <&qupv3_se1_2uart_sleep>;
> @@ -453,6 +477,20 @@
>                         };
>                 };
>
> +               system_noc: interconnect@1640000 {
> +                       compatible = "qcom,sdx75-system-noc";
> +                       reg = <0x0 0x01640000 0x0 0x4b400>;
> +                       #interconnect-cells = <2>;
> +                       qcom,bcm-voters = <&apps_bcm_voter>;
> +               };
> +
> +               pcie_anoc: interconnect@16c0000 {
> +                       compatible = "qcom,sdx75-pcie-anoc";
> +                       reg = <0x0 0x016c0000 0x0 0x14200>;
> +                       #interconnect-cells = <2>;
> +                       qcom,bcm-voters = <&apps_bcm_voter>;
> +               };
> +
>                 tcsr_mutex: hwlock@1f40000 {
>                         compatible = "qcom,tcsr-mutex";
>                         reg = <0x0 0x01f40000 0x0 0x40000>;
> @@ -733,6 +771,20 @@
>                         #freq-domain-cells = <1>;
>                         #clock-cells = <1>;
>                 };
> +
> +               dc_noc: interconnect@190e0000 {
> +                       compatible = "qcom,sdx75-dc-noc";
> +                       reg = <0x0 0x190e0000 0x0 0x8200>;
> +                       #interconnect-cells = <2>;
> +                       qcom,bcm-voters = <&apps_bcm_voter>;
> +               };
> +
> +               gem_noc: interconnect@19100000 {
> +                       compatible = "qcom,sdx75-gem-noc";
> +                       reg = <0x0 0x19100000 0x0 0x34080>;
> +                       #interconnect-cells = <2>;
> +                       qcom,bcm-voters = <&apps_bcm_voter>;
> +               };
>         };
>
>         timer {
> --
> 2.7.4
>
Rohit Agarwal Oct. 3, 2023, 10:52 a.m. UTC | #2 
On 10/3/2023 3:35 PM, Dmitry Baryshkov wrote:
> On Tue, 3 Oct 2023 at 13:04, Rohit Agarwal <quic_rohiagar@quicinc.com> wrote:
>> Add interconnect nodes to support interconnects on SDX75.
>> Also parallely add the interconnect property for UART required
>> so that the bootup to shell does not break with interconnects
>> in place.
>>
>> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sdx75.dtsi | 52 +++++++++++++++++++++++++++++++++++++
>>   1 file changed, 52 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
>> index e180aa4..ac0b785 100644
>> --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
>> @@ -8,6 +8,8 @@
>>
>>   #include <dt-bindings/clock/qcom,rpmh.h>
>>   #include <dt-bindings/clock/qcom,sdx75-gcc.h>
>> +#include <dt-bindings/interconnect/qcom,icc.h>
>> +#include <dt-bindings/interconnect/qcom,sdx75.h>
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   #include <dt-bindings/power/qcom,rpmhpd.h>
>>   #include <dt-bindings/power/qcom-rpmpd.h>
>> @@ -197,6 +199,19 @@
>>                  };
>>          };
>>
>> +       clk_virt: interconnect-0 {
>> +               compatible = "qcom,sdx75-clk-virt";
>> +               #interconnect-cells = <2>;
>> +               qcom,bcm-voters = <&apps_bcm_voter>;
>> +               clocks = <&rpmhcc RPMH_QPIC_CLK>;
>> +       };
>> +
>> +       mc_virt: interconnect-1 {
>> +               compatible = "qcom,sdx75-mc-virt";
>> +               #interconnect-cells = <2>;
>> +               qcom,bcm-voters = <&apps_bcm_voter>;
>> +       };
> Interconnect comes after firmware, 'i' > 'f'.
Will update this.

Thanks,
Rohit.
>
>> +
>>          firmware {
>>                  scm: scm {
>>                          compatible = "qcom,scm-sdx75", "qcom,scm";
>> @@ -434,6 +449,9 @@
>>                          clock-names = "m-ahb",
>>                                        "s-ahb";
>>                          iommus = <&apps_smmu 0xe3 0x0>;
>> +                       interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
>> +                                        &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
>> +                       interconnect-names = "qup-core";
>>                          #address-cells = <2>;
>>                          #size-cells = <2>;
>>                          ranges;
>> @@ -444,6 +462,12 @@
>>                                  reg = <0x0 0x00984000 0x0 0x4000>;
>>                                  clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
>>                                  clock-names = "se";
>> +                               interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
>> +                                                &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
>> +                                               <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>> +                                                &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
>> +                               interconnect-names = "qup-core",
>> +                                                    "qup-config";
>>                                  interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
>>                                  pinctrl-0 = <&qupv3_se1_2uart_active>;
>>                                  pinctrl-1 = <&qupv3_se1_2uart_sleep>;
>> @@ -453,6 +477,20 @@
>>                          };
>>                  };
>>
>> +               system_noc: interconnect@1640000 {
>> +                       compatible = "qcom,sdx75-system-noc";
>> +                       reg = <0x0 0x01640000 0x0 0x4b400>;
>> +                       #interconnect-cells = <2>;
>> +                       qcom,bcm-voters = <&apps_bcm_voter>;
>> +               };
>> +
>> +               pcie_anoc: interconnect@16c0000 {
>> +                       compatible = "qcom,sdx75-pcie-anoc";
>> +                       reg = <0x0 0x016c0000 0x0 0x14200>;
>> +                       #interconnect-cells = <2>;
>> +                       qcom,bcm-voters = <&apps_bcm_voter>;
>> +               };
>> +
>>                  tcsr_mutex: hwlock@1f40000 {
>>                          compatible = "qcom,tcsr-mutex";
>>                          reg = <0x0 0x01f40000 0x0 0x40000>;
>> @@ -733,6 +771,20 @@
>>                          #freq-domain-cells = <1>;
>>                          #clock-cells = <1>;
>>                  };
>> +
>> +               dc_noc: interconnect@190e0000 {
>> +                       compatible = "qcom,sdx75-dc-noc";
>> +                       reg = <0x0 0x190e0000 0x0 0x8200>;
>> +                       #interconnect-cells = <2>;
>> +                       qcom,bcm-voters = <&apps_bcm_voter>;
>> +               };
>> +
>> +               gem_noc: interconnect@19100000 {
>> +                       compatible = "qcom,sdx75-gem-noc";
>> +                       reg = <0x0 0x19100000 0x0 0x34080>;
>> +                       #interconnect-cells = <2>;
>> +                       qcom,bcm-voters = <&apps_bcm_voter>;
>> +               };
>>          };
>>
>>          timer {
>> --
>> 2.7.4
>>
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
index e180aa4..ac0b785 100644
--- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
@@ -8,6 +8,8 @@ 
 
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,sdx75.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/qcom,rpmhpd.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
@@ -197,6 +199,19 @@ 
 		};
 	};
 
+	clk_virt: interconnect-0 {
+		compatible = "qcom,sdx75-clk-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+		clocks = <&rpmhcc RPMH_QPIC_CLK>;
+	};
+
+	mc_virt: interconnect-1 {
+		compatible = "qcom,sdx75-mc-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
 	firmware {
 		scm: scm {
 			compatible = "qcom,scm-sdx75", "qcom,scm";
@@ -434,6 +449,9 @@ 
 			clock-names = "m-ahb",
 				      "s-ahb";
 			iommus = <&apps_smmu 0xe3 0x0>;
+			interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+					 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "qup-core";
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges;
@@ -444,6 +462,12 @@ 
 				reg = <0x0 0x00984000 0x0 0x4000>;
 				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 				clock-names = "se";
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
 				interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
 				pinctrl-0 = <&qupv3_se1_2uart_active>;
 				pinctrl-1 = <&qupv3_se1_2uart_sleep>;
@@ -453,6 +477,20 @@ 
 			};
 		};
 
+		system_noc: interconnect@1640000 {
+			compatible = "qcom,sdx75-system-noc";
+			reg = <0x0 0x01640000 0x0 0x4b400>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		pcie_anoc: interconnect@16c0000 {
+			compatible = "qcom,sdx75-pcie-anoc";
+			reg = <0x0 0x016c0000 0x0 0x14200>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
 		tcsr_mutex: hwlock@1f40000 {
 			compatible = "qcom,tcsr-mutex";
 			reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -733,6 +771,20 @@ 
 			#freq-domain-cells = <1>;
 			#clock-cells = <1>;
 		};
+
+		dc_noc: interconnect@190e0000 {
+			compatible = "qcom,sdx75-dc-noc";
+			reg = <0x0 0x190e0000 0x0 0x8200>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		gem_noc: interconnect@19100000 {
+			compatible = "qcom,sdx75-gem-noc";
+			reg = <0x0 0x19100000 0x0 0x34080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
 	};
 
 	timer {