| Message ID | 1696406908-9688-2-git-send-email-quic_rohiagar@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add devicetree support of Interconnects and USB for SDX75 | expand |
On 10/4/23 10:08, Rohit Agarwal wrote: > Add interconnect nodes to support interconnects on SDX75. > Also parallely add the interconnect property for UART required > so that the bootup to shell does not break with interconnects > in place. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sdx75.dtsi | 52 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 52 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi > index e180aa4..b4723fa 100644 > --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi > @@ -8,6 +8,8 @@ > > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/clock/qcom,sdx75-gcc.h> > +#include <dt-bindings/interconnect/qcom,icc.h> > +#include <dt-bindings/interconnect/qcom,sdx75.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/power/qcom,rpmhpd.h> > #include <dt-bindings/power/qcom-rpmpd.h> > @@ -203,6 +205,19 @@ > }; > }; > > + clk_virt: interconnect-0 { > + compatible = "qcom,sdx75-clk-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + clocks = <&rpmhcc RPMH_QPIC_CLK>; > + }; > + > + mc_virt: interconnect-1 { > + compatible = "qcom,sdx75-mc-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > memory@80000000 { > device_type = "memory"; > reg = <0x0 0x80000000 0x0 0x0>; > @@ -434,6 +449,9 @@ > clock-names = "m-ahb", > "s-ahb"; > iommus = <&apps_smmu 0xe3 0x0>; > + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core"; No qup-config? My brain compiler says this would cause a dt checker warning, at least on next-20231012. Konrad
On 10/12/2023 10:18 PM, Konrad Dybcio wrote: > > > On 10/4/23 10:08, Rohit Agarwal wrote: >> Add interconnect nodes to support interconnects on SDX75. >> Also parallely add the interconnect property for UART required >> so that the bootup to shell does not break with interconnects >> in place. >> >> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sdx75.dtsi | 52 >> +++++++++++++++++++++++++++++++++++++ >> 1 file changed, 52 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi >> b/arch/arm64/boot/dts/qcom/sdx75.dtsi >> index e180aa4..b4723fa 100644 >> --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi >> @@ -8,6 +8,8 @@ >> #include <dt-bindings/clock/qcom,rpmh.h> >> #include <dt-bindings/clock/qcom,sdx75-gcc.h> >> +#include <dt-bindings/interconnect/qcom,icc.h> >> +#include <dt-bindings/interconnect/qcom,sdx75.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> #include <dt-bindings/power/qcom,rpmhpd.h> >> #include <dt-bindings/power/qcom-rpmpd.h> >> @@ -203,6 +205,19 @@ >> }; >> }; >> + clk_virt: interconnect-0 { >> + compatible = "qcom,sdx75-clk-virt"; >> + #interconnect-cells = <2>; >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + clocks = <&rpmhcc RPMH_QPIC_CLK>; >> + }; >> + >> + mc_virt: interconnect-1 { >> + compatible = "qcom,sdx75-mc-virt"; >> + #interconnect-cells = <2>; >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + }; >> + >> memory@80000000 { >> device_type = "memory"; >> reg = <0x0 0x80000000 0x0 0x0>; >> @@ -434,6 +449,9 @@ >> clock-names = "m-ahb", >> "s-ahb"; >> iommus = <&apps_smmu 0xe3 0x0>; >> + interconnects = <&clk_virt MASTER_QUP_CORE_0 >> QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core"; > No qup-config? > > My brain compiler says this would cause a dt checker warning, at least > on next-20231012. If I check the tip, then there is only one interconnect entry. https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/soc/qcom/qcom%2Cgeni-se.yaml#L50 For the debug uart, the qup-config is added. I did check the dtbs_check before sending these patches. Please let me know if I am missing anything. Thanks, Rohit. > > Konrad
On 10/12/23 18:57, Rohit Agarwal wrote: > > On 10/12/2023 10:18 PM, Konrad Dybcio wrote: >> >> >> On 10/4/23 10:08, Rohit Agarwal wrote: >>> Add interconnect nodes to support interconnects on SDX75. >>> Also parallely add the interconnect property for UART required >>> so that the bootup to shell does not break with interconnects >>> in place. >>> >>> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/sdx75.dtsi | 52 >>> +++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 52 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi >>> b/arch/arm64/boot/dts/qcom/sdx75.dtsi >>> index e180aa4..b4723fa 100644 >>> --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi >>> @@ -8,6 +8,8 @@ >>> #include <dt-bindings/clock/qcom,rpmh.h> >>> #include <dt-bindings/clock/qcom,sdx75-gcc.h> >>> +#include <dt-bindings/interconnect/qcom,icc.h> >>> +#include <dt-bindings/interconnect/qcom,sdx75.h> >>> #include <dt-bindings/interrupt-controller/arm-gic.h> >>> #include <dt-bindings/power/qcom,rpmhpd.h> >>> #include <dt-bindings/power/qcom-rpmpd.h> >>> @@ -203,6 +205,19 @@ >>> }; >>> }; >>> + clk_virt: interconnect-0 { >>> + compatible = "qcom,sdx75-clk-virt"; >>> + #interconnect-cells = <2>; >>> + qcom,bcm-voters = <&apps_bcm_voter>; >>> + clocks = <&rpmhcc RPMH_QPIC_CLK>; >>> + }; >>> + >>> + mc_virt: interconnect-1 { >>> + compatible = "qcom,sdx75-mc-virt"; >>> + #interconnect-cells = <2>; >>> + qcom,bcm-voters = <&apps_bcm_voter>; >>> + }; >>> + >>> memory@80000000 { >>> device_type = "memory"; >>> reg = <0x0 0x80000000 0x0 0x0>; >>> @@ -434,6 +449,9 @@ >>> clock-names = "m-ahb", >>> "s-ahb"; >>> iommus = <&apps_smmu 0xe3 0x0>; >>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 >>> QCOM_ICC_TAG_ALWAYS >>> + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; >>> + interconnect-names = "qup-core"; >> No qup-config? >> >> My brain compiler says this would cause a dt checker warning, at least >> on next-20231012. > If I check the tip, then there is only one interconnect entry. > https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/soc/qcom/qcom%2Cgeni-se.yaml#L50 > For the debug uart, the qup-config is added. > I did check the dtbs_check before sending these patches. > Please let me know if I am missing anything. Oh, my brain compiler was correct, but for the wrong input data :) I thought you added this property to the UART itself, not to the QUP controller. Yes, you're right. Konrad
diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index e180aa4..b4723fa 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -8,6 +8,8 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sdx75-gcc.h> +#include <dt-bindings/interconnect/qcom,icc.h> +#include <dt-bindings/interconnect/qcom,sdx75.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/power/qcom-rpmpd.h> @@ -203,6 +205,19 @@ }; }; + clk_virt: interconnect-0 { + compatible = "qcom,sdx75-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + }; + + mc_virt: interconnect-1 { + compatible = "qcom,sdx75-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x0>; @@ -434,6 +449,9 @@ clock-names = "m-ahb", "s-ahb"; iommus = <&apps_smmu 0xe3 0x0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core"; #address-cells = <2>; #size-cells = <2>; ranges; @@ -444,6 +462,12 @@ reg = <0x0 0x00984000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; pinctrl-0 = <&qupv3_se1_2uart_active>; pinctrl-1 = <&qupv3_se1_2uart_sleep>; @@ -453,6 +477,20 @@ }; }; + system_noc: interconnect@1640000 { + compatible = "qcom,sdx75-system-noc"; + reg = <0x0 0x01640000 0x0 0x4b400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect@16c0000 { + compatible = "qcom,sdx75-pcie-anoc"; + reg = <0x0 0x016c0000 0x0 0x14200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -733,6 +771,20 @@ #freq-domain-cells = <1>; #clock-cells = <1>; }; + + dc_noc: interconnect@190e0000 { + compatible = "qcom,sdx75-dc-noc"; + reg = <0x0 0x190e0000 0x0 0x8200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@19100000 { + compatible = "qcom,sdx75-gem-noc"; + reg = <0x0 0x19100000 0x0 0x34080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; }; timer {
Add interconnect nodes to support interconnects on SDX75. Also parallely add the interconnect property for UART required so that the bootup to shell does not break with interconnects in place. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 52 +++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+)