From patchwork Tue Nov 21 02:24:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tao Zhang X-Patchwork-Id: 13462446 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="h118xkqb" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73C649C; Mon, 20 Nov 2023 18:25:43 -0800 (PST) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AL20lPM026928; Tue, 21 Nov 2023 02:25:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=KXHnq1zygstzXA4UPv3zVwIq7cSwIbUhPNRtSjCcP2I=; b=h118xkqbdvwFjQSXnYmthtL1yBvey23CUyFi11/JFA5sfozWeBKbAmpKIotysdA/C0cj UN2eyOarT4+Zvc0pVSNXV9CFH3VZltqvUmUKssXTAnCboRI6C3TDVwSFuLB+RrhH1iBI aQiTNVT4okCPb9rk1Kb5u3oO7NYk86WQK3gbvrhLA1HBfMWHNg/G+0L3KXazGBAy8vlT /AcTfyIbT2GixwQKhPzNoCkstdmlrAiBb3Tlk1PruK8dC+MiLSN+CinoAl+6vKopionk C5FCA2oE7TGs8OeWy5YOpHnIo4QX/ljVFxhsZhUl7W1YQgWBjk6W5C3MxROsImZcS91o xA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ugk6x0244-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Nov 2023 02:25:25 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AL2PNJ5008010 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Nov 2023 02:25:24 GMT Received: from taozha-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 20 Nov 2023 18:25:19 -0800 From: Tao Zhang To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Rob Herring , Krzysztof Kozlowski CC: Tao Zhang , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Song Chai , , Subject: [PATCH v3 1/8] dt-bindings: arm: Add support for CMB element size Date: Tue, 21 Nov 2023 10:24:47 +0800 Message-ID: <1700533494-19276-2-git-send-email-quic_taozha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1700533494-19276-1-git-send-email-quic_taozha@quicinc.com> References: <1700533494-19276-1-git-send-email-quic_taozha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Ob0bhh0m1RULO3Ws6mvCSaQxmTlKJ4uA X-Proofpoint-ORIG-GUID: Ob0bhh0m1RULO3Ws6mvCSaQxmTlKJ4uA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-20_22,2023-11-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 impostorscore=0 spamscore=0 clxscore=1015 adultscore=0 malwarescore=0 bulkscore=0 phishscore=0 priorityscore=1501 mlxlogscore=881 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311210015 Add property "qcom,cmb-elem-size" to support CMB(Continuous Multi-Bit) element for TPDM. The associated aggregator will read this size before it is enabled. CMB element size currently only supports 32-bit and 64-bit. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- .../bindings/arm/qcom,coresight-tpdm.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 61ddc3b5b247..0d9fe01a8b15 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -52,6 +52,15 @@ properties: $ref: /schemas/types.yaml#/definitions/uint8 enum: [32, 64] + qcom,cmb-element-size: + description: + Specifies the CMB(Continuous Multi-Bit) element size supported by + the monitor. The associated aggregator will read this size before it + is enabled. CMB element size currently only supports 8-bit, 32-bit + and 64-bit. + $ref: /schemas/types.yaml#/definitions/uint8 + enum: [8, 32, 64] + qcom,dsb-msrs-num: description: Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) @@ -110,4 +119,23 @@ examples: }; }; + tpdm@6c29000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x06c29000 0x1000>; + reg-names = "tpdm-base"; + + qcom,cmb-element-size = /bits/ 8 <64>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_out_funnel_center: endpoint { + remote-endpoint = + <&funnel_center_in_tpdm_ipcc>; + }; + }; + }; + }; ...