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Fri, 16 Jun 2023 19:02:58 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab%7]) with mapi id 15.20.6477.037; Fri, 16 Jun 2023 19:02:58 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Christophe Leroy , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kevin Tian , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Russell King , linuxppc-dev@lists.ozlabs.org, Matthias Brugger , Matthew Rosato , Michael Ellerman , Nicholas Piggin , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Dmitry Osipenko , Marek Szyprowski , Nicolin Chen , Niklas Schnelle , Steven Price , Thierry Reding Subject: [PATCH v4 02/25] iommu: Add IOMMU_DOMAIN_PLATFORM Date: Fri, 16 Jun 2023 16:02:31 -0300 Message-Id: <2-v4-874277bde66e+1a9f6-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v4-874277bde66e+1a9f6-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: BLAPR03CA0064.namprd03.prod.outlook.com (2603:10b6:208:329::9) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|SJ1PR12MB6051:EE_ X-MS-Office365-Filtering-Correlation-Id: 7ebf6e83-3cda-46ec-ddac-08db6e9c4aec X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UK/a6fMwYmb913nD1igr94THvMguKmcos2SExBxWZQGMjBMsDjOaETvlVI+eoZ/+BUbAOTWnPgarELYrjwsNRbGooRiNhxvObviAaAlJurTFczc8NQVARB2rGsreqOcEVqLB4vRr83eigdMeetOKPRXFGzC/3rkd1pN2/U3ZTvEnV8bCsC0bPBuRKcXfyDt+nQoO+mQkWqO8sU8Il9BHw1stzlUtTSUip3T4VzMp/ybwIMtK6wknCp7YKWezlXyv97iikKPIc3A++evGIEJmTisx2fptHuAWIxXhjJdYH3hmkkFoYczW/7LYTvh4sDevyvr3yo1zZ8ilIqdtMHtRKUorO4yTI0XTi91P9SDSkOgKiyTNiEJAtPHPvhzAG2OpdEjkWmFycxpPRrlXwjXAmzoE4b3LYp1zQWDN0whJcPWvaMqHw0vy+kk/LYNJvmy5dGwPaO7soD3V6stOJpVG9gh4mQZaxO+KtGp13H3Y7PBmff85OPTdShxuCqnjySHrC1HAcJuSxbq86psgZ0JZsQ319YMEJaRTDepQ0aCPrDUt5EMgUKcU5GWm7gagahyn27U+/F2CcX2aMCgxVq58/V6gyZlmjpcS2PU4XlQTG6nQC0HGOyv7Sd4hVY7eksm90vOTzxxXX06F5D/o8h1PTJbB+HGRraM40/EQ5XT7oQPR00mpRziw666N7fl9Famyozw68RRxaez1rk0m3RT7EfjXzjD6Mj2glfIX1r3u24CDANP0lwiWAeT3vKAw2d4s0s2Kf8xHb2joBnva51Jv31K20wgoziBaMLvQbcL1erOItGnESHFR+A6lzuUVZIYjAzFS5hZWe+qyJ+h5ZcWKqyBqtC0dlmD68f7UdT+cVIlYraQY432L29l032S+e6DWsut+1qf8LovRqre6YpvTcog7UqOtNV6xO09G2ZxHLfuLdUwiq0LWIAtqNgQurS9DZ2Yjm532WZi80wKstPLiKpFutxNSvN9iflQZGLXWu4QBYZvTE6JXlzYf0/wUXBznS8OqKkNGzszShcFZrhxrPjR0vwMBCsRcuIkYjevn+gtZGN7slPBte0pmGukSo+jDxc4/0vT1o+gpCJruseZSvda1Nni11KJVj8tEMPRmEz4WWysGSwiO9OK2pohJKwvnFiXTiWfF1GXoK6L3EK+YMN4HsLpZ8YzDP4WTAcCSTaiQJ9mA8b6CF+6BJ6UVr1QnSDd5KHdBga4a8fXCThwXI0k/uUE2xkUmKT1kHFUmIAhSLPX+fg3ZvAmH0AxXir6s6+3mVailxsX97Hh2O0ZiGFkmV18INB7ip/IvQv1J6tpGlA0fOxCUvNU3XcYRMJXYjZNvmnCMS24KxZqdF1QblQv+nkeyUdPNiQ3c70imLfxUkG1/1M9Gq8qae2/z/ryVYX62fxogRVJDJJxtya6VHrWJbtRXWOt3EB3kDXPQ6By4r9XwzH9k3Sl/GWBM0OhS+m9xa2TaAo9A/is5Jgvm4k9vgaZpU9p+P1FW6sjIt2FsH587BPGxKZc9t5pC8HDUujdyxkJS05Q2d+jbqDZgNL47dfAJehARupNNSjMlrBiG9YLkjotpape+U5pPO2os X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7ebf6e83-3cda-46ec-ddac-08db6e9c4aec X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2023 19:02:55.5605 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: A2Ctpc48InBh1CR88+GYB6ZZCxFIG0VeYri6jzytF8Iosqo7NQYV39vk+l+RxVAK X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6051 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This is used when the iommu driver is taking control of the dma_ops, currently only on S390 and power spapr. It is designed to preserve the original ops->detach_dev() semantic that these S390 was built around. Provide an opaque domain type and a 'default_domain' ops value that allows the driver to trivially force any single domain as the default domain. Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 14 +++++++++++++- include/linux/iommu.h | 6 ++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index bb840a818525ad..c8f6664767152d 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1644,6 +1644,17 @@ iommu_group_alloc_default_domain(struct iommu_group *group, int req_type) lockdep_assert_held(&group->mutex); + /* + * Allow legacy drivers to specify the domain that will be the default + * domain. This should always be either an IDENTITY or PLATFORM domain. + * Do not use in new drivers. + */ + if (bus->iommu_ops->default_domain) { + if (req_type) + return ERR_PTR(-EINVAL); + return bus->iommu_ops->default_domain; + } + if (req_type) return __iommu_group_alloc_default_domain(bus, group, req_type); @@ -1953,7 +1964,8 @@ void iommu_domain_free(struct iommu_domain *domain) if (domain->type == IOMMU_DOMAIN_SVA) mmdrop(domain->mm); iommu_put_dma_cookie(domain); - domain->ops->free(domain); + if (domain->ops->free) + domain->ops->free(domain); } EXPORT_SYMBOL_GPL(iommu_domain_free); diff --git a/include/linux/iommu.h b/include/linux/iommu.h index c3004eac2f88e8..ef0a0000f09326 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -64,6 +64,7 @@ struct iommu_domain_geometry { #define __IOMMU_DOMAIN_DMA_FQ (1U << 3) /* DMA-API uses flush queue */ #define __IOMMU_DOMAIN_SVA (1U << 4) /* Shared process address space */ +#define __IOMMU_DOMAIN_PLATFORM (1U << 5) #define IOMMU_DOMAIN_ALLOC_FLAGS ~__IOMMU_DOMAIN_DMA_FQ /* @@ -81,6 +82,8 @@ struct iommu_domain_geometry { * invalidation. * IOMMU_DOMAIN_SVA - DMA addresses are shared process addresses * represented by mm_struct's. + * IOMMU_DOMAIN_PLATFORM - Legacy domain for drivers that do their own + * dma_api stuff. Do not use in new drivers. */ #define IOMMU_DOMAIN_BLOCKED (0U) #define IOMMU_DOMAIN_IDENTITY (__IOMMU_DOMAIN_PT) @@ -91,6 +94,7 @@ struct iommu_domain_geometry { __IOMMU_DOMAIN_DMA_API | \ __IOMMU_DOMAIN_DMA_FQ) #define IOMMU_DOMAIN_SVA (__IOMMU_DOMAIN_SVA) +#define IOMMU_DOMAIN_PLATFORM (__IOMMU_DOMAIN_PLATFORM) struct iommu_domain { unsigned type; @@ -256,6 +260,7 @@ struct iommu_iotlb_gather { * @owner: Driver module providing these ops * @identity_domain: An always available, always attachable identity * translation. + * @default_domain: If not NULL this will always be set as the default domain. */ struct iommu_ops { bool (*capable)(struct device *dev, enum iommu_cap); @@ -290,6 +295,7 @@ struct iommu_ops { unsigned long pgsize_bitmap; struct module *owner; struct iommu_domain *identity_domain; + struct iommu_domain *default_domain; }; /**