From patchwork Wed Sep 7 21:35:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 9319987 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EAEA2607D3 for ; Wed, 7 Sep 2016 21:36:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 03CCE29290 for ; Wed, 7 Sep 2016 21:36:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EC12929434; Wed, 7 Sep 2016 21:36:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C745B29290 for ; Wed, 7 Sep 2016 21:36:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934648AbcIGVgo (ORCPT ); Wed, 7 Sep 2016 17:36:44 -0400 Received: from mail-pf0-f174.google.com ([209.85.192.174]:36006 "EHLO mail-pf0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757468AbcIGVfq (ORCPT ); Wed, 7 Sep 2016 17:35:46 -0400 Received: by mail-pf0-f174.google.com with SMTP id 128so10401875pfb.3 for ; Wed, 07 Sep 2016 14:35:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Zv9m2zYov9bDaSIZbT7FT1LA3b5pRLLqyLOne8nZVag=; b=g8JtZc2zsiVoig6AoV2DPrj09pr2z/AORuSYokUioVJxqfZ7eBx7aVgjLeeS07Se49 q6O9I7Sm2IAw0JibzRCNwzX8HnWY7AZCJ9qEmk4/PwJpdpv824bgvfVRpKBqzK6SUfCB TGc/uJp6vWbh+tPJvgMHrppqjuinyv9+Pz1eo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Zv9m2zYov9bDaSIZbT7FT1LA3b5pRLLqyLOne8nZVag=; b=HyFV5Sj+c2UmQd7bvMJlsVr7hrwasB//oo/oHxJ3LmMfdqfmIKmERB8gjlt0gdZsp8 X/opFehlyxtyzH+I9AZAyZ0KrTIcR/nUtNgO0RRd61lLVCppWEPFQWaR5OsPOWWIh+f9 YTKGRua+8IgA3pGTEJC02pLslCh4hnSBLCbmubTLUBTGpAYFEzH56LXlm0GDrtkZjVt6 DvSJQd++7YH0L7dk3nm7Fo3DzDJhM2hDsLU09Ofd3owbtKUj28pDViNuzFmcpPpXnpKO dhGWoUP4srBoXYrLrhUx5Nan0kwSVneBLnbgFDHqE1HcTgCpxoKChqtSrQrWlR5KQP75 RDKw== X-Gm-Message-State: AE9vXwN8OGUd5SskJNqo9TLnt9umYiSFVUaj2NIv/wYWgbOm7hjFezCgFHetuqPKEOD3G9So X-Received: by 10.98.130.137 with SMTP id w131mr85720172pfd.5.1473284140396; Wed, 07 Sep 2016 14:35:40 -0700 (PDT) Received: from localhost.localdomain (ip68-101-172-78.sd.sd.cox.net. [68.101.172.78]) by smtp.gmail.com with ESMTPSA id 75sm51015417pfw.92.2016.09.07.14.35.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Sep 2016 14:35:40 -0700 (PDT) From: Stephen Boyd To: linux-usb@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Andy Gross , Bjorn Andersson , Neil Armstrong , Arnd Bergmann , Felipe Balbi , Peter Chen , Greg Kroah-Hartman Subject: [PATCH v4 15/22] usb: chipidea: msm: Mux over secondary phy at the right time Date: Wed, 7 Sep 2016 14:35:12 -0700 Message-Id: <20160907213519.27340-16-stephen.boyd@linaro.org> X-Mailer: git-send-email 2.9.0.rc2.8.ga28705d In-Reply-To: <20160907213519.27340-1-stephen.boyd@linaro.org> References: <20160907213519.27340-1-stephen.boyd@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We need to pick the correct phy at runtime based on how the SoC has been wired onto the board. If the secondary phy is used, take it out of reset and mux over to it by writing into the TCSR register. Make sure to do this on reset too, because this register is reset to the default value (primary phy) after the RESET bit is set in USBCMD. Acked-by: Peter Chen Cc: Greg Kroah-Hartman Signed-off-by: Stephen Boyd --- drivers/usb/chipidea/ci_hdrc_msm.c | 62 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 60 insertions(+), 2 deletions(-) diff --git a/drivers/usb/chipidea/ci_hdrc_msm.c b/drivers/usb/chipidea/ci_hdrc_msm.c index 7e870a253f55..4b0aadc2be2f 100644 --- a/drivers/usb/chipidea/ci_hdrc_msm.c +++ b/drivers/usb/chipidea/ci_hdrc_msm.c @@ -8,29 +8,44 @@ #include #include #include -#include #include #include #include +#include +#include +#include #include "ci.h" #define HS_PHY_AHB_MODE 0x0098 +/* Vendor base starts at 0x200 beyond CI base */ +#define HS_PHY_SEC_CTRL 0x0078 +#define HS_PHY_DIG_CLAMP_N BIT(16) + struct ci_hdrc_msm { struct platform_device *ci; struct clk *core_clk; struct clk *iface_clk; struct clk *fs_clk; + bool secondary_phy; + void __iomem *base; }; static void ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event) { - struct device *dev = ci->gadget.dev.parent; + struct device *dev = ci->dev->parent; + struct ci_hdrc_msm *msm_ci = dev_get_drvdata(dev); switch (event) { case CI_HDRC_CONTROLLER_RESET_EVENT: dev_dbg(dev, "CI_HDRC_CONTROLLER_RESET_EVENT received\n"); + if (msm_ci->secondary_phy) { + u32 val = readl_relaxed(msm_ci->base + HS_PHY_SEC_CTRL); + val |= HS_PHY_DIG_CLAMP_N; + writel_relaxed(val, msm_ci->base + HS_PHY_SEC_CTRL); + } + /* use AHB transactor, allow posted data writes */ hw_write_id_reg(ci, HS_PHY_AHB_MODE, 0xffffffff, 0x8); usb_phy_init(ci->usb_phy); @@ -59,6 +74,39 @@ static struct ci_hdrc_platform_data ci_hdrc_msm_platdata = { .notify_event = ci_hdrc_msm_notify_event, }; +static int ci_hdrc_msm_mux_phy(struct ci_hdrc_msm *ci, + struct platform_device *pdev) +{ + struct regmap *regmap; + struct device *dev = &pdev->dev; + struct of_phandle_args args; + u32 val; + int ret; + + ret = of_parse_phandle_with_fixed_args(dev->of_node, "phy-select", 2, 0, + &args); + if (ret) + return 0; + + regmap = syscon_node_to_regmap(args.np); + of_node_put(args.np); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + ret = regmap_write(regmap, args.args[0], args.args[1]); + if (ret) + return ret; + + ci->secondary_phy = !!args.args[1]; + if (ci->secondary_phy) { + val = readl_relaxed(ci->base + HS_PHY_SEC_CTRL); + val |= HS_PHY_DIG_CLAMP_N; + writel_relaxed(val, ci->base + HS_PHY_SEC_CTRL); + } + + return 0; +} + static int ci_hdrc_msm_probe(struct platform_device *pdev) { struct ci_hdrc_msm *ci; @@ -66,6 +114,7 @@ static int ci_hdrc_msm_probe(struct platform_device *pdev) struct usb_phy *phy; struct clk *clk; struct reset_control *reset; + struct resource *res; int ret; dev_dbg(&pdev->dev, "ci_hdrc_msm_probe\n"); @@ -105,6 +154,11 @@ static int ci_hdrc_msm_probe(struct platform_device *pdev) ci->fs_clk = NULL; } + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + ci->base = devm_ioremap_resource(&pdev->dev, res); + if (!ci->base) + return -ENOMEM; + ret = clk_prepare_enable(ci->fs_clk); if (ret) return ret; @@ -123,6 +177,10 @@ static int ci_hdrc_msm_probe(struct platform_device *pdev) if (ret) goto err_iface; + ret = ci_hdrc_msm_mux_phy(ci, pdev); + if (ret) + goto err_mux; + plat_ci = ci_hdrc_add_device(&pdev->dev, pdev->resource, pdev->num_resources, &ci_hdrc_msm_platdata);