From patchwork Thu Mar 23 10:28:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Archit Taneja X-Patchwork-Id: 9640765 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 98EF7601E9 for ; Thu, 23 Mar 2017 10:30:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9A7AA28438 for ; Thu, 23 Mar 2017 10:30:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F6A9284A5; Thu, 23 Mar 2017 10:30:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 223C028438 for ; Thu, 23 Mar 2017 10:30:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933251AbdCWKaF (ORCPT ); Thu, 23 Mar 2017 06:30:05 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:58428 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933242AbdCWKaF (ORCPT ); Thu, 23 Mar 2017 06:30:05 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id AC3316110E; Thu, 23 Mar 2017 10:29:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1490265003; bh=cRFCbeCKBqxpjhjoR1RnhMLjP3QzBgP0IlOPF1y4ldY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lQgXHL94Y6i7ECKeHLQjQaAvTlRCjxn7/HP1oAs1nrlaqAM3zQLX57ul4j9VbmFEq xcXmoeSApwGeqXKFAS3PUx1DuN+hzzJfBoTofyhjn2bGx9RjQO6o6NWjUxvSOIfVm8 kHzztP3o4YoBUDrcjgTwKkhkX/jtnXwSsXooxbpI= Received: from localhost (unknown [202.46.23.61]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: architt@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4B0FD60D94; Thu, 23 Mar 2017 10:29:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1490264996; bh=cRFCbeCKBqxpjhjoR1RnhMLjP3QzBgP0IlOPF1y4ldY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PSzZOkM7YVs9LoB1FrEETmqZIm77oLsxefyUWf7TecdZ6sbmh1XQJtXiKzG0ebCYR +JG2q6O0dQgNTBBdILmGeDT8OtYE+GVG4sXf15XH1TqNIOazvvtFPUQxcdSmp+E10c e/xCxpPwFYLWOn6eV0iczDU0jl5wreSnZDCQ7THE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4B0FD60D94 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=architt@codeaurora.org From: Archit Taneja To: robdclark@gmail.com Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Archit Taneja Subject: [PATCH 21/24] drm/msm/mdp5: Stage border out on base stage if CRTC has 2 LMs Date: Thu, 23 Mar 2017 15:58:14 +0530 Message-Id: <20170323102817.15017-22-architt@codeaurora.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170323102817.15017-1-architt@codeaurora.org> References: <20170323102817.15017-1-architt@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If a CRTC comprises of 2 LMs, it is mandatory to enable border out and assign it to the base stage. We had to enable border out also when the base plane wasn't fullscreen. Club these checks and put them in a separate function called get_start_stage() that returns the starting stage for assigning planes. Signed-off-by: Archit Taneja --- drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 45 +++++++++++++++++++++++++------- 1 file changed, 35 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c index cf6d41c9edc7..d0559962f85b 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c @@ -518,6 +518,29 @@ static bool is_fullscreen(struct drm_crtc_state *cstate, ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay); } +enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc, + struct drm_crtc_state *new_crtc_state, + struct drm_plane_state *bpstate) +{ + struct mdp5_crtc_state *mdp5_cstate = + to_mdp5_crtc_state(new_crtc_state); + + /* + * if we're in source split mode, it's mandatory to have + * border out on the base stage + */ + if (mdp5_cstate->pipeline.r_mixer) + return STAGE0; + + /* if the bottom-most layer is not fullscreen, we need to use + * it for solid-color: + */ + if (!is_fullscreen(new_crtc_state, bpstate)) + return STAGE0; + + return STAGE_BASE; +} + static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) { @@ -528,8 +551,9 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, const struct mdp5_cfg_hw *hw_cfg; const struct drm_plane_state *pstate; bool cursor_plane = false; - int cnt = 0, base = 0, i; + int cnt = 0, i; int ret; + enum mdp_mixer_stage_id start; DBG("%s: check", crtc->name); @@ -543,6 +567,10 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, cursor_plane = true; } + /* bail out early if there aren't any planes */ + if (!cnt) + return 0; + ret = mdp5_crtc_setup_pipeline(crtc, state); if (ret) { dev_err(dev->dev, "couldn't assign mixers %d\n", ret); @@ -552,23 +580,20 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, /* assign a stage based on sorted zpos property */ sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); - /* if the bottom-most layer is not fullscreen, we need to use - * it for solid-color: - */ - if ((cnt > 0) && !is_fullscreen(state, &pstates[0].state->base)) - base++; - /* trigger a warning if cursor isn't the highest zorder */ WARN_ON(cursor_plane && (pstates[cnt - 1].plane->type != DRM_PLANE_TYPE_CURSOR)); + start = get_start_stage(crtc, state, &pstates[0].state->base); + /* verify that there are not too many planes attached to crtc * and that we don't have conflicting mixer stages: */ hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); - if ((cnt + base) >= hw_cfg->lm.nb_stages) { - dev_err(dev->dev, "too many planes! cnt=%d, base=%d\n", cnt, base); + if ((cnt + start - 1) >= hw_cfg->lm.nb_stages) { + dev_err(dev->dev, "too many planes! cnt=%d, start stage=%d\n", + cnt, start); return -EINVAL; } @@ -576,7 +601,7 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, if (cursor_plane && (i == (cnt - 1))) pstates[i].state->stage = hw_cfg->lm.nb_stages; else - pstates[i].state->stage = STAGE_BASE + i + base; + pstates[i].state->stage = start + i; DBG("%s: assign pipe %s on stage=%d", crtc->name, pstates[i].plane->name, pstates[i].state->stage);