From patchwork Thu Mar 23 10:28:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Archit Taneja X-Patchwork-Id: 9640775 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C4EAE601E9 for ; Thu, 23 Mar 2017 10:30:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C723D2847F for ; Thu, 23 Mar 2017 10:30:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BC5B8284C2; Thu, 23 Mar 2017 10:30:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6798A2847F for ; Thu, 23 Mar 2017 10:30:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933262AbdCWKaS (ORCPT ); Thu, 23 Mar 2017 06:30:18 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:58752 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933242AbdCWKaS (ORCPT ); Thu, 23 Mar 2017 06:30:18 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7962F61152; Thu, 23 Mar 2017 10:30:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1490265016; bh=CMueS5g7Lg6aFTdd62Efk7VlSow/4mw0YbfQxFaHYXo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cHzhcGhdoxXkhHZ4taKmCLILoh+McBdAZr/V0eg4/P9g6WywIs8eiHD+GvK+DfXvk uM+U8eU5liRuUkPnMnFlZwvmxKsKRvphGUgUyBAYMcosWoMCKfhzFuddm8q8Qfor7q UtJeU9imLP/WFyq1h5KupFu1yROfrS8FMxy7DgjY= Received: from localhost (unknown [202.46.23.61]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: architt@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2228F61157; Thu, 23 Mar 2017 10:30:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1490265010; bh=CMueS5g7Lg6aFTdd62Efk7VlSow/4mw0YbfQxFaHYXo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G2GnxNZzaXhysR6foKDqt4guFU2xef5qvGWc8NADSxa5Rc43onu1cgTEpVGaR+HX2 /tdi5amEWuyQ0Yn0qxgL2kDKIFhqyL4lYRBuhoGNeNBU66z/BN8Q/aZfMZyCQWV/Nq 5jh8Y6iYVNapuPEP84SmGO+6t3q0UzmZd+lcFTdE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2228F61157 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=architt@codeaurora.org From: Archit Taneja To: robdclark@gmail.com Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Archit Taneja Subject: [PATCH 24/24] drm/msm/mdp5: Enable 3D mux in mdp5_ctl Date: Thu, 23 Mar 2017 15:58:17 +0530 Message-Id: <20170323102817.15017-25-architt@codeaurora.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170323102817.15017-1-architt@codeaurora.org> References: <20170323102817.15017-1-architt@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP 3D mux is a small block placed after the DSPPs in MDP5. It can merge 2 LM/DSPP outputs and feed it to a single interface. Enable 3D Mux if our mdp5_pipeline has 2 active LMs. This check will need to be made more specific later when we add Dual DSI support with source split enabled. In that use case, each LM feeds to a separae INTF, so the 3D mux isn't needed. Signed-off-by: Archit Taneja --- drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c index fddde84afdc3..439e0a300e25 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c @@ -138,9 +138,10 @@ static void set_display_intf(struct mdp5_kms *mdp5_kms, spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); } -static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_interface *intf) +static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) { unsigned long flags; + struct mdp5_interface *intf = pipeline->intf; u32 ctl_op = 0; if (!mdp5_cfg_intf_is_virtual(intf->type)) @@ -161,6 +162,10 @@ static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_interface *intf) break; } + if (pipeline->r_mixer) + ctl_op |= MDP5_CTL_OP_PACK_3D_ENABLE | + MDP5_CTL_OP_PACK_3D(1); + spin_lock_irqsave(&ctl->hw_lock, flags); ctl_write(ctl, REG_MDP5_CTL_OP(ctl->id), ctl_op); spin_unlock_irqrestore(&ctl->hw_lock, flags); @@ -183,7 +188,7 @@ int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) if (!mdp5_cfg_intf_is_virtual(intf->type)) set_display_intf(mdp5_kms, intf); - set_ctl_op(ctl, intf); + set_ctl_op(ctl, pipeline); return 0; }