From patchwork Thu May 25 17:33:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 9748817 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id ACDDF60209 for ; Thu, 25 May 2017 17:34:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 95A7427B81 for ; Thu, 25 May 2017 17:34:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8A51B27F4B; Thu, 25 May 2017 17:34:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1EB8627B81 for ; Thu, 25 May 2017 17:34:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936532AbdEYReA (ORCPT ); Thu, 25 May 2017 13:34:00 -0400 Received: from mail-qt0-f196.google.com ([209.85.216.196]:36293 "EHLO mail-qt0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751923AbdEYRd6 (ORCPT ); Thu, 25 May 2017 13:33:58 -0400 Received: by mail-qt0-f196.google.com with SMTP id j13so31026182qta.3; Thu, 25 May 2017 10:33:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=L2am5D3g4u4+y5IJ64y96/lLnfjKSc2yR49nMiNc/X4=; b=JhjIJA1CHwhiXZW0VtSJhH9r2lJZ/ze0WxXr5kibzlO+DXbz1N/ckByhgyq21ojVgX Fa5VpLJaw1e9SHALRk24kfg6mzvb1D9rfXqCbl971J0a8ErRVhefqtpPV/jy2t/V8jm6 n79KduPxmDn4dWqnNtDt9Mmsqzw7epb5xGzilYHLwi373Snkxok+9IVAA8CI1LIzM/vU vIr7IAp6gzeivNo9PnApPolhtMpzuwscR64TWO6fTcnB4bzpIvFr0otLSE8t+vgpHNsr h46+jlgPoPVT4mlJKiZ1khF0lWyO+ruDqJ8/q7/ug8rc5iI2i4Fl6hddB2wnedNpot2d CZFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=L2am5D3g4u4+y5IJ64y96/lLnfjKSc2yR49nMiNc/X4=; b=PNBV85Wu7SaLiuUn5hzyVzO+ZzcxfjC5mbATpvLSt0SVJ4AxwhyAzAPr9W0SM9LvoU hEbc7Kr3j75ycgqDuOSZVNv4DEOxhYCTPdnDv8VlU4FH1qFDkS6mOCBQ1Z/mtEYswwXz iPEm+wMW01P7SGF8iCgfQHU11NIVwQf4GyshyDJLiVO6Wwe38v4EVApQzCh18Znh65Mw lrn3Ku4eekYZu6FPWY0tGA0sgzBvdUvEVh4JwvBtIEOb0Pt2XS5SUlJMfQdPdfDSZ5yU sAgxp4K2dWywt4fgv6hDmE4Umhc0pPVIZFHSxoyNpCpu6X7sO6mxCWo1rxGR9Rf8GHsH B2Dg== X-Gm-Message-State: AODbwcAW14OIppKCYOMuFxC8SeS/FrLG5m0B487Zwno6AFgaaTpgYweW aA0OmtD7GtPGlA== X-Received: by 10.200.47.73 with SMTP id k9mr41818551qta.11.1495733637278; Thu, 25 May 2017 10:33:57 -0700 (PDT) Received: from localhost (nat-pool-bos-t.redhat.com. [66.187.233.206]) by smtp.gmail.com with ESMTPSA id x49sm5167435qth.5.2017.05.25.10.33.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 25 May 2017 10:33:55 -0700 (PDT) From: Rob Clark To: iommu@lists.linux-foundation.org Cc: linux-arm-msm@vger.kernel.org, Rob Herring , Robin Murphy , Will Deacon , Sricharan , Mark Rutland , Stanimir Varbanov , Archit Taneja , Rob Clark , devicetree@vger.kernel.org Subject: [PATCH 1/4] Docs: dt: document qcom iommu bindings Date: Thu, 25 May 2017 13:33:37 -0400 Message-Id: <20170525173340.26904-2-robdclark@gmail.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170525173340.26904-1-robdclark@gmail.com> References: <20170525173340.26904-1-robdclark@gmail.com> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Cc: devicetree@vger.kernel.org Signed-off-by: Rob Clark Reviewed-by: Rob Herring --- .../devicetree/bindings/iommu/qcom,iommu.txt | 121 +++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/qcom,iommu.txt diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt new file mode 100644 index 0000000..0d50f84 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt @@ -0,0 +1,121 @@ +* QCOM IOMMU v1 Implementation + +Qualcomm "B" family devices which are not compatible with arm-smmu have +a similar looking IOMMU but without access to the global register space, +and optionally requiring additional configuration to route context irqs +to non-secure vs secure interrupt line. + +** Required properties: + +- compatible : Should be one of: + + "qcom,msm8916-iommu" + + Followed by "qcom,msm-iommu-v1". + +- clock-names : Should be a pair of "iface" (required for IOMMUs + register group access) and "bus" (required for + the IOMMUs underlying bus access). + +- clocks : Phandles for respective clocks described by + clock-names. + +- #address-cells : must be 1. + +- #size-cells : must be 1. + +- #iommu-cells : Must be 1. + +- ranges : Base address and size of the iommu context banks. + +- qcom,iommu-secure-id : secure-id. + +- List of sub-nodes, one per translation context bank. Each sub-node + has the following required properties: + + - compatible : Should be one of: + - "qcom,msm-iommu-v1-ns" : non-secure context bank + - "qcom,msm-iommu-v1-sec" : secure context bank + - reg : Base address and size of context bank within the iommu + - interrupts : The context fault irq. + +** Optional properties: + +- reg : Base address and size of the SMMU local base, should + be only specified if the iommu requires configuration + for routing of context bank irq's to secure vs non- + secure lines. (Ie. if the iommu contains secure + context banks) + + +** Examples: + + apps_iommu: iommu@1e20000 { + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x1e20000 0x40000>; + reg = <0x1ef0000 0x3000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <17>; + + // mdp_0: + iommu-ctx@4000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x4000 0x1000>; + interrupts = ; + }; + + // venus_ns: + iommu-ctx@5000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x5000 0x1000>; + interrupts = ; + }; + }; + + gpu_iommu: iommu@1f08000 { + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x1f08000 0x10000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <18>; + + // gfx3d_user: + iommu-ctx@1f09000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + // gfx3d_priv: + iommu-ctx@1f0a000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + }; + + ... + + venus: video-codec@1d00000 { + ... + iommus = <&apps_iommu 5>; + }; + + mdp: mdp@1a01000 { + ... + iommus = <&apps_iommu 4>; + }; + + gpu@01c00000 { + ... + iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + };