From patchwork Fri Nov 17 02:39:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 10062251 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 73FC86023A for ; Fri, 17 Nov 2017 02:40:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 541FA2A8C8 for ; Fri, 17 Nov 2017 02:40:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 481FF2A8D7; Fri, 17 Nov 2017 02:40:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 35CB62A8C8 for ; Fri, 17 Nov 2017 02:40:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932311AbdKQCkA (ORCPT ); Thu, 16 Nov 2017 21:40:00 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:34738 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932080AbdKQCj7 (ORCPT ); Thu, 16 Nov 2017 21:39:59 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D07CF6071C; Fri, 17 Nov 2017 02:39:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1510886398; bh=B+7FrXmvjZmwG8cURQ3RC1LOfzBvu3a9yF+qLwZSjuw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=fMbD83Lx/QmauMEGdgg5iM6oCKwOQbVFfDCkgZquHYJyEZUJfuy8IGkZLuxABTyXA tmYbX6mG6JO9kJ6ee2PmCDLBgY6EmnvGEON2fAcNx14ROTRiBhGaQ9NaFPtpQtaics z7RuFLEjI00njo84u9nFrsC39rh8Z0NF+hU2tmvc= Received: from localhost (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: sboyd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1E3D8601CF; Fri, 17 Nov 2017 02:39:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1510886398; bh=B+7FrXmvjZmwG8cURQ3RC1LOfzBvu3a9yF+qLwZSjuw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=fMbD83Lx/QmauMEGdgg5iM6oCKwOQbVFfDCkgZquHYJyEZUJfuy8IGkZLuxABTyXA tmYbX6mG6JO9kJ6ee2PmCDLBgY6EmnvGEON2fAcNx14ROTRiBhGaQ9NaFPtpQtaics z7RuFLEjI00njo84u9nFrsC39rh8Z0NF+hU2tmvc= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1E3D8601CF Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Thu, 16 Nov 2017 18:39:57 -0800 From: Stephen Boyd To: Catalin Marinas Cc: Will Deacon , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] arm64: cpu_errata: Add Kryo to Falkor 1003 errata Message-ID: <20171117023957.GT11955@codeaurora.org> References: <20171108190029.19835-1-sboyd@codeaurora.org> <20171110172656.zvnpfjkky7rqumyf@armageddon.cambridge.arm.com> <20171115003522.GL11955@codeaurora.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20171115003522.GL11955@codeaurora.org> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 11/14, Stephen Boyd wrote: > On 11/10, Catalin Marinas wrote: > > On Wed, Nov 08, 2017 at 11:00:29AM -0800, Stephen Boyd wrote: > > > The Kryo CPUs are also affected by the Falkor 1003 errata, so > > > we need to do the same workaround on Kryo CPUs. The MIDR is > > > slightly more complicated here, where the PART number is not > > > always the same when looking at all the bits from 15 to 4. Drop > > > the lower 8 bits and just look at the top 4 to see if it's '2' > > > and then consider those as Kryo CPUs. This covers all the > > > combinations without having to list them all out. > > > > > > Signed-off-by: Stephen Boyd > > > --- > > > > > > We may need to introduce another Kconfig option to block software PAN > > > from being enabled when this errata is enabled (and then have software PAN > > > depend on this new config being false). > > > > It depends on whether you'd want to use SW PAN together with these CPUs. > > From a defconfig + single Image perspective, SW PAN is disabled but it > > would be nice to allow single Image with both E1003 and SW PAN configs > > enabled (though SW PAN wouldn't be used at run-time). > > > > As a quick hack, something like below but we may want to add a separate > > cap bit as a minor optimisation (not sure it makes a difference). > > Untested: > > Ok. The Falkor CPUs support HW PAN so your patch looks like it > should work. If we're running on a Kryo CPU we may not see the HW > PAN capability and then we would still return false here because > the errata is present. I'll fold it in and test it out. Almost works. The problem is that uaccess_ttbr0_{disable,enable} assembly macros need to be patched for NOPs if we have cap bits for ARM64_HAS_PAN or ARM64_WORKAROUND_QCOM_FALKOR_E1003. From what I can tell, we have only ever had one bit there so doing something like: ----8<---- won't work just like that because it's not a bitmask, just a raw cap number. So I need to introduce another capability number that combines the presence of HW_PAN and this errata? Looks like it would be similar to ARM64_ALT_PAN_NOT_UAO. diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h index b3da6c886835..70644cde9e7c 100644 --- a/arch/arm64/include/asm/asm-uaccess.h +++ b/arch/arm64/include/asm/asm-uaccess.h @@ -26,13 +26,13 @@ .endm .macro uaccess_ttbr0_disable, tmp1 -alternative_if_not ARM64_HAS_PAN +alternative_if_not (ARM64_HAS_PAN | ARM64_WORKAROUND_QCOM_FALKOR_E1003) __uaccess_ttbr0_disable \tmp1 alternative_else_nop_endif .endm .macro uaccess_ttbr0_enable, tmp1, tmp2 -alternative_if_not ARM64_HAS_PAN +alternative_if_not (ARM64_HAS_PAN | ARM64_WORKAROUND_QCOM_FALKOR_E1003) save_and_disable_irq \tmp2 // avoid preemption __uaccess_ttbr0_enable \tmp1 restore_irq \tmp2