From patchwork Thu Jan 25 16:32:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 10184341 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DA7C160388 for ; Thu, 25 Jan 2018 16:33:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA84728999 for ; Thu, 25 Jan 2018 16:33:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BEE032899C; Thu, 25 Jan 2018 16:33:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 414DC28999 for ; Thu, 25 Jan 2018 16:33:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750994AbeAYQdY (ORCPT ); Thu, 25 Jan 2018 11:33:24 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:44884 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751255AbeAYQcd (ORCPT ); Thu, 25 Jan 2018 11:32:33 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 32F4660A96; Thu, 25 Jan 2018 16:32:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516897953; bh=Bp3/3WT2OyXgUcAdCqo0obqVAPxCF+SGMUdrFWLv+Ig=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XBDciHWa6udHMvSuBtqLkMERhainEFRGrB8N3wI4gakZ89afxO5EZEHyyuOsVzoEp wEtZHbrEuJNWFtI9jVKnDGuS6PTXEIKGIqyypvIJ1gEMkCdzRhtGhwgYzLnnbVO3sM Xvx4YYNn/ChvsPZnXM3yqzko786cVc7wYeVEcBhI= Received: from blr-ubuntu-173.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.1 with cipher ECDHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E1846607EB; Thu, 25 Jan 2018 16:32:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516897952; bh=Bp3/3WT2OyXgUcAdCqo0obqVAPxCF+SGMUdrFWLv+Ig=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cBPjfrJ+Cqk2+/8nU/APa817EvXb866YNooqb+qne1E23QBuvyLNp6HMtomFF4y+Q lQYGw/LGgKfUry0okE5y2sz/WnN2K+AV3DPYdBL6zSSZX+cw9Zzm5D+QazhmYU7iSG 5JPiWQVYOtURPHsrTdab8B94tTY6MkxYtFlfbvAo= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E1846607EB Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: andy.gross@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Rajendra Nayak Subject: [PATCH 2/2] arm64: dts: sdm845: Add serial console support Date: Thu, 25 Jan 2018 22:02:16 +0530 Message-Id: <20180125163216.29018-3-rnayak@codeaurora.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180125163216.29018-1-rnayak@codeaurora.org> References: <20180125163216.29018-1-rnayak@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the qup uart node and geni se instance needed to support the serial console on the MTP. Signed-off-by: Rajendra Nayak --- This patch is based on the current proposed DT bindings for the geni based serial driver [1] and also depends on the GCC driver [2] which adds dt-bindings/clock/qcom,gcc-sdm845.h header. This can only be merged once the dependent patches do. [1] https://patchwork.ozlabs.org/cover/860251/ [2] https://lkml.org/lkml/2018/1/22/78 arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi | 3 +++ arch/arm64/boot/dts/qcom/sdm845-pins.dtsi | 32 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 22 +++++++++++++++++++++ 3 files changed, 57 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-pins.dtsi diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi b/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi index 5b1022c20bad..640a48cd628b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi @@ -7,5 +7,8 @@ / { soc { + serial@a84000 { + status = "okay"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-pins.dtsi b/arch/arm64/boot/dts/qcom/sdm845-pins.dtsi new file mode 100644 index 000000000000..b97f99e6f4b4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-pins.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +&tlmm { + qup_uart2_default: qup_uart2_default { + pinmux { + function = "qup9"; + pins = "gpio4", "gpio5"; + }; + + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_uart2_sleep: qup_uart2_sleep { + pinmux { + function = "gpio"; + pins = "gpio4", "gpio5"; + }; + + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index a21f4912b3e2..529f4ba3a1db 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4,6 +4,7 @@ */ #include +#include / { model = "Qualcomm Technologies, Inc. SDM845"; @@ -304,5 +305,26 @@ cell-index = <0>; }; + qup_1: qcom,geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x6000>; + }; + + qup_uart2: serial@a84000 { + compatible = "qcom,geni-console", "qcom,geni-uart"; + reg = <0xa84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_uart2_default>; + pinctrl-1 = <&qup_uart2_sleep>; + interrupts = ; + qcom,wrapper-core = <&qup_1>; + status = "disabled"; + }; }; }; +#include "sdm845-pins.dtsi"