From patchwork Fri Mar 16 04:08:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 10286369 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5442260386 for ; Fri, 16 Mar 2018 04:10:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4DC0028D24 for ; Fri, 16 Mar 2018 04:10:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4284B28D35; Fri, 16 Mar 2018 04:10:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D311128D24 for ; Fri, 16 Mar 2018 04:10:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751511AbeCPEI4 (ORCPT ); Fri, 16 Mar 2018 00:08:56 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:49118 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751468AbeCPEIw (ORCPT ); Fri, 16 Mar 2018 00:08:52 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 0B85F60F5C; Fri, 16 Mar 2018 04:08:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521173332; bh=ZzJvfGWuXSxCau+UnW3adfQmofogiAou/s3iS+35KIc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j+JwrNZW/DDzWu7WMC1uE6qMjEeZFiPAW7aqXlNScgGnY9QdBUV9h5bg+RrCo72Y6 cKF5AAL+FilrpSYbq+CWGG+TLA1YTS5JD33/EncUtt6CnDPhgs8aOmFeDxvySjNHy6 xN3ZfSzRfoCzrMil46q7i+CvwDXYgRge1GrEt6ro= Received: from blr-ubuntu-173.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.1 with cipher ECDHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2407360C5F; Fri, 16 Mar 2018 04:08:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521173331; bh=ZzJvfGWuXSxCau+UnW3adfQmofogiAou/s3iS+35KIc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XA2W0SwMIa8CBDxNT0gbY6tHj1G/WMst+0pMk0lR5atNb9PvOYGTI0Hx2R8idLHjO HyW8JKHTU10lLtL6/bkSQL8dbs6utGk0hiuwC0GMf7Io6DTTusoNAJJ0ieEO45bAN4 47am6UOkQiSuIl+XJEouHwiVBKoBsGS1vhH6mYn0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2407360C5F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: viresh.kumar@linaro.org, sboyd@kernel.org, andy.gross@linaro.org, ulf.hansson@linaro.org Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Rajendra Nayak Subject: [PATCH 3/7] dt-bindings: opp: Introduce qcom-opp bindings Date: Fri, 16 Mar 2018 09:38:20 +0530 Message-Id: <20180316040824.21472-4-rnayak@codeaurora.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180316040824.21472-1-rnayak@codeaurora.org> References: <20180316040824.21472-1-rnayak@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Qualcomm platforms, an OPP node needs to describe an additional level/corner value that is then communicated to a remote microprocessor by the CPU, which then takes some actions (like adjusting voltage values across various rails) based on the value passed. Describe these bindings in the qcom-opp bindings document. Signed-off-by: Rajendra Nayak Acked-by: Viresh Kumar Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/opp/qcom-opp.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/opp/qcom-opp.txt diff --git a/Documentation/devicetree/bindings/opp/qcom-opp.txt b/Documentation/devicetree/bindings/opp/qcom-opp.txt new file mode 100644 index 000000000000..56fe87751881 --- /dev/null +++ b/Documentation/devicetree/bindings/opp/qcom-opp.txt @@ -0,0 +1,25 @@ +Qualcomm OPP bindings to descibe OPP nodes with corner/level values + +OPP tables for devices on qualcomm platforms require an additional +platform specific corner/level value to be specified. +This value is passed on to the RPM (Resource Power Manager) by +the CPU, which then takes the necessary actions to set a voltage +rail to a appropriate voltage based on the value passed. + +The bindings are based on top of the operating-points-v2 bindings +described in Documentation/devicetree/bindings/opp/opp.txt +Additional properties are described below. + +* OPP Table Node + +Required properties: +- compatible: Allow OPPs to express their compatibility. It should be: + "operating-points-v2-qcom" + +* OPP Node + +Required properties: +- qcom,level: On Qualcomm platforms an OPP node can describe a positive value +representing a corner/level thats comminicated with a remote microprocessor +(Usually called the RPM) which then translates it into a certain voltage on +a voltage rail.