From patchwork Tue Jun 12 04:40:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 10459273 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D33E2603B4 for ; Tue, 12 Jun 2018 04:42:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C3AC62863B for ; Tue, 12 Jun 2018 04:42:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B786B28640; Tue, 12 Jun 2018 04:42:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 653CF2863B for ; Tue, 12 Jun 2018 04:42:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932800AbeFLElZ (ORCPT ); Tue, 12 Jun 2018 00:41:25 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:35732 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932592AbeFLElX (ORCPT ); Tue, 12 Jun 2018 00:41:23 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 92FF1606DB; Tue, 12 Jun 2018 04:41:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1528778482; bh=oltgX3MV2Km3blGMQjBAhFbOERkJWYDc0oNmCOPMe8E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Se7L2WQEaqFYVJXD/kPCkj8uTXiODtlNGCLOLu/N/DyyH2BY7VXzzb7UbbF1s8G2G Y7SFZcyfGaVUmAGx9AICHg6PN1KngCArigUeeg6MNt9F5XgFAAr1yTTqib09BtUNgq rQSh8L2QWvhl0pCxszptt5BVQn6xNSnCdx5Nr7VI= Received: from blr-ubuntu-173.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2769E602BD; Tue, 12 Jun 2018 04:41:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1528778482; bh=oltgX3MV2Km3blGMQjBAhFbOERkJWYDc0oNmCOPMe8E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Se7L2WQEaqFYVJXD/kPCkj8uTXiODtlNGCLOLu/N/DyyH2BY7VXzzb7UbbF1s8G2G Y7SFZcyfGaVUmAGx9AICHg6PN1KngCArigUeeg6MNt9F5XgFAAr1yTTqib09BtUNgq rQSh8L2QWvhl0pCxszptt5BVQn6xNSnCdx5Nr7VI= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2769E602BD Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: viresh.kumar@linaro.org, sboyd@kernel.org, andy.gross@linaro.org, ulf.hansson@linaro.org, collinsd@codeaurora.org Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Rajendra Nayak Subject: [PATCH v3 5/7] dt-bindings: power: Add qcom rpmh power domain driver bindings Date: Tue, 12 Jun 2018 10:10:50 +0530 Message-Id: <20180612044052.4402-6-rnayak@codeaurora.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180612044052.4402-1-rnayak@codeaurora.org> References: <20180612044052.4402-1-rnayak@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add DT bindings to describe the rpmh powerdomains found on Qualcomm Technologies, Inc. SoCs. These power domains communicate a performance state to RPMh, which then translates it into corresponding voltage on a PMIC rail. Signed-off-by: Rajendra Nayak --- .../devicetree/bindings/power/qcom,rpmhpd.txt | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/qcom,rpmhpd.txt diff --git a/Documentation/devicetree/bindings/power/qcom,rpmhpd.txt b/Documentation/devicetree/bindings/power/qcom,rpmhpd.txt new file mode 100644 index 000000000000..41ef7afa6b24 --- /dev/null +++ b/Documentation/devicetree/bindings/power/qcom,rpmhpd.txt @@ -0,0 +1,65 @@ +Qualcomm RPMh Power domains + +For RPMh Power domains, we communicate a performance state to RPMh +which then translates it into a corresponding voltage on a rail + +Required Properties: + - compatible: Should be one of the following + * qcom,sdm845-rpmhpd: RPMh Power domain for the sdm845 family of SoC + - power-domain-cells: number of cells in power domain specifier + must be 1 + - operating-points-v2: Phandle to the OPP table for the power-domain. + Refer to Documentation/devicetree/bindings/power/power_domain.txt + and Documentation/devicetree/bindings/opp/qcom-opp.txt for more details + +Example: + + rpmhpd: power-controller { + compatible = "qcom,sdm845-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + }; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2-qcom-level"; + + rpmhpd_opp_ret: opp1 { + qcom-level = <16>; + }; + + rpmhpd_opp_min_svs: opp2 { + qcom-level = <48>; + }; + + rpmhpd_opp_low_svs: opp3 { + qcom-level = <64>; + }; + + rpmhpd_opp_svs: opp4 { + qcom-level = <128>; + }; + + rpmhpd_opp_svs_l1: opp5 { + qcom-level = <192>; + }; + + rpmhpd_opp_nom: opp6 { + qcom-level = <256>; + }; + + rpmhpd_opp_nom_l1: opp7 { + qcom-level = <320>; + }; + + rpmhpd_opp_nom_l2: opp8 { + qcom-level = <336>; + }; + + rpmhpd_opp_turbo: opp9 { + qcom-level = <384>; + }; + + rpmhpd_opp_turbo_l1: opp10 { + qcom-level = <416>; + }; + };