From patchwork Wed Jun 20 20:48:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Paul X-Patchwork-Id: 10478705 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EB26260383 for ; Wed, 20 Jun 2018 20:48:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DB17C28355 for ; Wed, 20 Jun 2018 20:48:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CFB13283A5; Wed, 20 Jun 2018 20:48:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B6AA28355 for ; Wed, 20 Jun 2018 20:48:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933308AbeFTUsx (ORCPT ); Wed, 20 Jun 2018 16:48:53 -0400 Received: from mail-yw0-f196.google.com ([209.85.161.196]:38277 "EHLO mail-yw0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933283AbeFTUsw (ORCPT ); Wed, 20 Jun 2018 16:48:52 -0400 Received: by mail-yw0-f196.google.com with SMTP id w13-v6so344111ywa.5 for ; Wed, 20 Jun 2018 13:48:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9iu2E2FhOVcni3/EbWsZqrtL29z0pdzcuN7F5cIWll8=; b=nHOO42D40TyklZzk786fBzJI1ztnoA4ouH94fwUqZRd/JKPuMdI9sXjv6BMzKvrNoB JHiJzAteYpr3AuY3zFLJDRWvF/AKzLnVa2J+ao72c4GF8wDL2i//i1V0jWrJ/6VvSXer wjkqP3K678HOWkXnB3RoIriU+j7C62Sv0tPNk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9iu2E2FhOVcni3/EbWsZqrtL29z0pdzcuN7F5cIWll8=; b=K2PL5SOSHcdVojD0nZRTzIW3ByoLaPqDSPjZvWSmMPu1G5NY8F3T5nJNlGpbLo8dsJ jk5bIQsU4zHzSnqBclikLqjjwAtn4LHMtoKHAkgSV54Vqi+0udJJ22eBGOKhb5ADz9VH NRivtfz4cU0SEjKoLsT/m9TN4jPxYuq1uuhNoVOMlbf9hVQmFPEW5YyMOd7dAcjdfkVr JTYFG3rN+JUOQbBsNloFBsczo5KSlJDqkfIstFc6LkiOJdU9Sv0kV8zU1w5MwZFoFlfa teNhgoEAIi70tYtwZBS0qgHxzjkgxeRJkmNRTGaHbFtIF9osfxJi8c1S1RA+CD5JPBEZ l4nw== X-Gm-Message-State: APt69E23RrmVIGCub8oDr6h3tIb5G/KyYOOZpw5Q2dzAuMz4KVKVgYh3 fpk6Obt+9SaTo9ckZyWeLo4S+EVA5no= X-Google-Smtp-Source: ADUXVKJhoj9vx0OL01jhDIZDNVvuNG1xjVe8HDuoDzfQjgPz6jRTsgQ/iOMiGX4hAhfNZ6MmhfKwig== X-Received: by 2002:a81:3c0d:: with SMTP id j13-v6mr10503579ywa.16.1529527731600; Wed, 20 Jun 2018 13:48:51 -0700 (PDT) Received: from rosewood.cam.corp.google.com ([2620:0:1013:11:ad55:b1db:adfe:3b9f]) by smtp.gmail.com with ESMTPSA id p3-v6sm1173865ywh.36.2018.06.20.13.48.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Jun 2018 13:48:51 -0700 (PDT) From: Sean Paul To: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Cc: robdclark@gmail.com, hoegsberg@chromium.org, jsanka@codeaurora.org, abhinavk@codeaurora.org, Sean Paul Subject: [DPU PATCH 10/19] drm/msm: dpu_core_irq: Replace DPU_EVT with tracepoints Date: Wed, 20 Jun 2018 16:48:32 -0400 Message-Id: <20180620204841.56354-11-seanpaul@chromium.org> X-Mailer: git-send-email 2.18.0.rc1.244.gcf134e6275-goog In-Reply-To: <20180620204841.56354-1-seanpaul@chromium.org> References: <20180620204841.56354-1-seanpaul@chromium.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch converts all DPU_EVTs in dpu_core_irq with either a DRM_* log message or a linux tracepoint. Signed-off-by: Sean Paul Reviewed-by: Rajesh Yadav --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 52 ++++++++------------ drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 50 +++++++++++++++++++ 2 files changed, 71 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c index 33ab2ac46833..530c24dec017 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c @@ -18,6 +18,7 @@ #include #include "dpu_core_irq.h" +#include "dpu_trace.h" /** * dpu_core_irq_callback_handler - dispatch core interrupts @@ -34,10 +35,8 @@ static void dpu_core_irq_callback_handler(void *arg, int irq_idx) pr_debug("irq_idx=%d\n", irq_idx); if (list_empty(&irq_obj->irq_cb_tbl[irq_idx])) { - DPU_ERROR("irq_idx=%d has no registered callback\n", irq_idx); - DPU_EVT32_IRQ(irq_idx, atomic_read( - &dpu_kms->irq_obj.enable_counts[irq_idx]), - DPU_EVTLOG_ERROR); + DRM_ERROR("no registered cb, idx:%d enable_count:%d\n", irq_idx, + atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx])); } atomic_inc(&irq_obj->irq_counts[irq_idx]); @@ -80,7 +79,7 @@ int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms, static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int irq_idx) { unsigned long irq_flags; - int ret = 0; + int ret = 0, enable_count; if (!dpu_kms || !dpu_kms->hw_intr || !dpu_kms->irq_obj.enable_counts || @@ -94,11 +93,10 @@ static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int irq_idx) return -EINVAL; } - DPU_DEBUG("irq_idx=%d enable_count=%d\n", irq_idx, - atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx])); + enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]); + DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count); + trace_dpu_core_irq_enable_idx(irq_idx, enable_count); - DPU_EVT32(irq_idx, - atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx])); if (atomic_inc_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 1) { ret = dpu_kms->hw_intr->ops.enable_irq( dpu_kms->hw_intr, @@ -130,11 +128,8 @@ int dpu_core_irq_enable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count) } counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]); - if (counts) { - DPU_ERROR("%pS: irq_idx=%d enable_count=%d\n", - __builtin_return_address(0), irq_idxs[0], counts); - DPU_EVT32(irq_idxs[0], counts, DPU_EVTLOG_ERROR); - } + if (counts) + DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts); for (i = 0; (i < irq_count) && !ret; i++) ret = _dpu_core_irq_enable(dpu_kms, irq_idxs[i]); @@ -149,7 +144,7 @@ int dpu_core_irq_enable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count) */ static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms, int irq_idx) { - int ret = 0; + int ret = 0, enable_count; if (!dpu_kms || !dpu_kms->hw_intr || !dpu_kms->irq_obj.enable_counts) { DPU_ERROR("invalid params\n"); @@ -161,11 +156,10 @@ static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms, int irq_idx) return -EINVAL; } - DPU_DEBUG("irq_idx=%d enable_count=%d\n", irq_idx, - atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx])); + enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]); + DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count); + trace_dpu_core_irq_disable_idx(irq_idx, enable_count); - DPU_EVT32(irq_idx, - atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx])); if (atomic_dec_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 0) { ret = dpu_kms->hw_intr->ops.disable_irq( dpu_kms->hw_intr, @@ -189,11 +183,8 @@ int dpu_core_irq_disable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count) } counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]); - if (counts == 2) { - DPU_ERROR("%pS: irq_idx=%d enable_count=%d\n", - __builtin_return_address(0), irq_idxs[0], counts); - DPU_EVT32(irq_idxs[0], counts, DPU_EVTLOG_ERROR); - } + if (counts == 2) + DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts); for (i = 0; (i < irq_count) && !ret; i++) ret = _dpu_core_irq_disable(dpu_kms, irq_idxs[i]); @@ -209,7 +200,7 @@ int dpu_core_irq_disable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count) */ int dpu_core_irq_disable_nolock(struct dpu_kms *dpu_kms, int irq_idx) { - int ret = 0; + int ret = 0, enable_count; if (!dpu_kms || !dpu_kms->hw_intr || !dpu_kms->irq_obj.enable_counts) { DPU_ERROR("invalid params\n"); @@ -221,11 +212,10 @@ int dpu_core_irq_disable_nolock(struct dpu_kms *dpu_kms, int irq_idx) return -EINVAL; } - DPU_DEBUG("irq_idx=%d enable_count=%d\n", irq_idx, - atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx])); + enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]); + DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count); + trace_dpu_core_irq_disable_nolock(irq_idx, enable_count); - DPU_EVT32(irq_idx, - atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx])); if (atomic_dec_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 0) { ret = dpu_kms->hw_intr->ops.disable_irq_nolock( dpu_kms->hw_intr, @@ -297,7 +287,7 @@ int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms, int irq_idx, DPU_DEBUG("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx); spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags); - DPU_EVT32(irq_idx, register_irq_cb); + trace_dpu_core_irq_register_callback(irq_idx, register_irq_cb); list_del_init(®ister_irq_cb->list); list_add_tail(®ister_irq_cb->list, &dpu_kms->irq_obj.irq_cb_tbl[irq_idx]); @@ -332,7 +322,7 @@ int dpu_core_irq_unregister_callback(struct dpu_kms *dpu_kms, int irq_idx, DPU_DEBUG("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx); spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags); - DPU_EVT32(irq_idx, register_irq_cb); + trace_dpu_core_irq_unregister_callback(irq_idx, register_irq_cb); list_del_init(®ister_irq_cb->list); /* empty callback list but interrupt is still enabled */ if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]) && diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index 9d044f5ce26e..ee41db86a2e9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -966,6 +966,56 @@ TRACE_EVENT(dpu_pp_connect_ext_te, TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg) ); +DECLARE_EVENT_CLASS(dpu_core_irq_idx_cnt_template, + TP_PROTO(int irq_idx, int enable_count), + TP_ARGS(irq_idx, enable_count), + TP_STRUCT__entry( + __field( int, irq_idx ) + __field( int, enable_count ) + ), + TP_fast_assign( + __entry->irq_idx = irq_idx; + __entry->enable_count = enable_count; + ), + TP_printk("irq_idx:%d enable_count:%u", __entry->irq_idx, + __entry->enable_count) +); +DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_enable_idx, + TP_PROTO(int irq_idx, int enable_count), + TP_ARGS(irq_idx, enable_count) +); +DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_disable_idx, + TP_PROTO(int irq_idx, int enable_count), + TP_ARGS(irq_idx, enable_count) +); +DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_disable_nolock, + TP_PROTO(int irq_idx, int enable_count), + TP_ARGS(irq_idx, enable_count) +); + +DECLARE_EVENT_CLASS(dpu_core_irq_callback_template, + TP_PROTO(int irq_idx, struct dpu_irq_callback *callback), + TP_ARGS(irq_idx, callback), + TP_STRUCT__entry( + __field( int, irq_idx ) + __field( struct dpu_irq_callback *, callback) + ), + TP_fast_assign( + __entry->irq_idx = irq_idx; + __entry->callback = callback; + ), + TP_printk("irq_idx:%d callback:%pK", __entry->irq_idx, + __entry->callback) +); +DEFINE_EVENT(dpu_core_irq_callback_template, dpu_core_irq_register_callback, + TP_PROTO(int irq_idx, struct dpu_irq_callback *callback), + TP_ARGS(irq_idx, callback) +); +DEFINE_EVENT(dpu_core_irq_callback_template, dpu_core_irq_unregister_callback, + TP_PROTO(int irq_idx, struct dpu_irq_callback *callback), + TP_ARGS(irq_idx, callback) +); + #define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0) #define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1) #define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)