From patchwork Wed Jun 20 20:48:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Paul X-Patchwork-Id: 10478723 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6B33960383 for ; Wed, 20 Jun 2018 20:49:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B31528355 for ; Wed, 20 Jun 2018 20:49:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5003D283A5; Wed, 20 Jun 2018 20:49:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 978E528355 for ; Wed, 20 Jun 2018 20:49:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933351AbeFTUtA (ORCPT ); Wed, 20 Jun 2018 16:49:00 -0400 Received: from mail-yw0-f196.google.com ([209.85.161.196]:38284 "EHLO mail-yw0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933283AbeFTUs6 (ORCPT ); Wed, 20 Jun 2018 16:48:58 -0400 Received: by mail-yw0-f196.google.com with SMTP id w13-v6so344233ywa.5 for ; Wed, 20 Jun 2018 13:48:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=U8P/o9sYwEmE8QGpB4973hUFPUrVJqOgbJ42gSqwv+0=; b=F5oX8HuVWAVRG4OkBJ9sR8SuyEpxTqmTWdvzK6rCRHvqAeQ18cwHEpot8AzBi8jK+n KWw1YFbohSJNsGcgLvP9N9CTHmSsr4LIBXteFmQUMcc1jYIQ8Ba9D+ZyVDLYvhOklUF6 eRG50aSJaJg7sGAiKUwwwQiadB81Fc1pKqS4s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=U8P/o9sYwEmE8QGpB4973hUFPUrVJqOgbJ42gSqwv+0=; b=bI9vNvqz4K+0z6ZgyKm0BN5TlFCIoq9NcB4I4bMMKcJJx8VGPkHSG8HsZBDqwE3dMJ NKTPSJPcZFFnuAixcZtS4lbgkq5xR15n5tVvUP2dYwzMf5u5HWtnWgMadmJNQnCxLfQk /Mzc20BuE6/tVC7cteuiqeMszCFtToj1vVdHQw5UxypOOcP/28kThO2/HMw82E1oxAtz nj70rqGeMzB3phdWGFKc6me0zEZzadz8sJSGmpKdaohXJYqBGXFr8yANmZmUfLUO4b60 N4QhkVNEu1gT/I1PFpkqUWH0JK8xbUA4V4GVF5DlQsaTDfIOZhJ0/aGnFCZhZuRPNkHl hwbQ== X-Gm-Message-State: APt69E03k7mW/PLN94AGJHC9vszG73AhdfF19y5wbAKHf4BYJqHh0W44 eJLu+JP01lLbYN+9PYcjr7h6aVfQ8WM= X-Google-Smtp-Source: ADUXVKKgNxsdpPz2pw1jIrAaIALlD7Sv7V+KkHD9Y1ws4jOt6u6pSugKmF5V2cmRBPUPJ/y8NgkK+A== X-Received: by 2002:a81:d303:: with SMTP id y3-v6mr10860549ywi.490.1529527738298; Wed, 20 Jun 2018 13:48:58 -0700 (PDT) Received: from rosewood.cam.corp.google.com ([2620:0:1013:11:ad55:b1db:adfe:3b9f]) by smtp.gmail.com with ESMTPSA id p3-v6sm1173865ywh.36.2018.06.20.13.48.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Jun 2018 13:48:57 -0700 (PDT) From: Sean Paul To: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Cc: robdclark@gmail.com, hoegsberg@chromium.org, jsanka@codeaurora.org, abhinavk@codeaurora.org, Sean Paul Subject: [DPU PATCH 18/19] drm/msm: dpu_dbg: Remove string parsing from DBG_DUMP Date: Wed, 20 Jun 2018 16:48:40 -0400 Message-Id: <20180620204841.56354-19-seanpaul@chromium.org> X-Mailer: git-send-email 2.18.0.rc1.244.gcf134e6275-goog In-Reply-To: <20180620204841.56354-1-seanpaul@chromium.org> References: <20180620204841.56354-1-seanpaul@chromium.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Now that we don't have arbitrary register dumping, remove the macro and just call dpu_dbg_dump directly. Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +- drivers/gpu/drm/msm/dpu_dbg.c | 37 +++++-------------- drivers/gpu/drm/msm/dpu_dbg.h | 23 ++++-------- 5 files changed, 21 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 3519f7e84f0f..ce4faee12adc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1563,7 +1563,7 @@ void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) rc = ctl->ops.reset(ctl); if (rc) { DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); - DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus"); + dpu_dbg_dump(false, __func__, true, true); } phys_enc->enable_state = DPU_ENC_ENABLED; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 19f5b5064ed8..9519dbc24266 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -262,7 +262,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( atomic_read(&phys_enc->pending_kickoff_cnt)); dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR); - DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus"); + dpu_dbg_dump(false, __func__, true, true); } atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 54f4e78cf1fd..110c463077ed 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -638,7 +638,7 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff( DPU_ERROR_VIDENC(vid_enc, "ctl %d reset failure: %d\n", ctl->idx, rc); dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC); - DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus"); + dpu_dbg_dump(false, __func__, true, true); } } diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c index 51d46975cc27..ae2aee7ed9e1 100644 --- a/drivers/gpu/drm/msm/dpu_dbg.c +++ b/drivers/gpu/drm/msm/dpu_dbg.c @@ -2248,39 +2248,22 @@ static void _dpu_dump_work(struct work_struct *work) dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work); } -void dpu_dbg_dump(bool queue_work, const char *name, ...) +void dpu_dbg_dump(bool queue_work, const char *name, bool dump_dbgbus_dpu, + bool dump_dbgbus_vbif_rt) { - bool dump_dbgbus_dpu = false; - bool dump_dbgbus_vbif_rt = false; - va_list args; - char *blk_name = NULL; - if (queue_work && work_pending(&dpu_dbg_base.dump_work)) return; - va_start(args, name); - while ((blk_name = va_arg(args, char*))) { - if (IS_ERR_OR_NULL(blk_name)) - break; - - if (!strcmp(blk_name, "dbg_bus")) - dump_dbgbus_dpu = true; - - if (!strcmp(blk_name, "vbif_dbg_bus")) - dump_dbgbus_vbif_rt = true; - } - va_end(args); - - if (queue_work) { - /* schedule work to dump later */ - dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work = - dump_dbgbus_dpu; - dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work = - dump_dbgbus_vbif_rt; - schedule_work(&dpu_dbg_base.dump_work); - } else { + if (!queue_work) { _dpu_dump_array(name, dump_dbgbus_dpu, dump_dbgbus_vbif_rt); + return; } + + /* schedule work to dump later */ + dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work = dump_dbgbus_dpu; + dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work = + dump_dbgbus_vbif_rt; + schedule_work(&dpu_dbg_base.dump_work); } /* diff --git a/drivers/gpu/drm/msm/dpu_dbg.h b/drivers/gpu/drm/msm/dpu_dbg.h index 6a247ce39997..05504e676f6a 100644 --- a/drivers/gpu/drm/msm/dpu_dbg.h +++ b/drivers/gpu/drm/msm/dpu_dbg.h @@ -22,14 +22,6 @@ enum dpu_dbg_dump_flag { DPU_DBG_DUMP_IN_MEM = BIT(1), }; -/** - * DPU_DBG_DUMP - trigger dumping of all dpu_dbg facilities - * @va_args: list of named register dump ranges and regions to dump, as - * registered previously through dpu_dbg_reg_register_base and - * dpu_dbg_reg_register_dump_range. - */ -#define DPU_DBG_DUMP(...) dpu_dbg_dump(false, __func__, ##__VA_ARGS__, NULL) - #if defined(CONFIG_DEBUG_FS) /** @@ -60,14 +52,14 @@ void dpu_dbg_destroy(void); /** * dpu_dbg_dump - trigger dumping of all dpu_dbg facilities - * @queue_work: whether to queue the dumping work to the work_struct - * @name: string indicating origin of dump - * @va_args: list of named register dump ranges and regions to dump, as - * registered previously through dpu_dbg_reg_register_base and - * dpu_dbg_reg_register_dump_range. + * @queue_work: whether to queue the dumping work to the work_struct + * @name: string indicating origin of dump + * @dump_dbgbus: dump the dpu debug bus + * @dump_vbif_rt: dump the vbif rt bus * Returns: none */ -void dpu_dbg_dump(bool queue_work, const char *name, ...); +void dpu_dbg_dump(bool queue_work, const char *name, bool dump_dbgbus_dpu, + bool dump_dbgbus_vbif_rt); /** * dpu_dbg_set_dpu_top_offset - set the target specific offset from mdss base @@ -105,7 +97,8 @@ static inline void dpu_dbg_destroy(void) { } -static inline void dpu_dbg_dump(bool queue_work, const char *name, ...) +static inline void dpu_dbg_dump(bool queue_work, const char *name, + bool dump_dbgbus_dpu, bool dump_dbgbus_vbif_rt); { }