From patchwork Wed Jun 20 20:48:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Paul X-Patchwork-Id: 10478703 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D78D960532 for ; Wed, 20 Jun 2018 20:48:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C855C28355 for ; Wed, 20 Jun 2018 20:48:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BCEC1283A5; Wed, 20 Jun 2018 20:48:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9B72B28355 for ; Wed, 20 Jun 2018 20:48:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933274AbeFTUsu (ORCPT ); Wed, 20 Jun 2018 16:48:50 -0400 Received: from mail-yb0-f169.google.com ([209.85.213.169]:40993 "EHLO mail-yb0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933154AbeFTUst (ORCPT ); Wed, 20 Jun 2018 16:48:49 -0400 Received: by mail-yb0-f169.google.com with SMTP id e16-v6so357977ybh.8 for ; Wed, 20 Jun 2018 13:48:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yWHX9Q4LJTGZZowk5cb3ZATvK5oUhAswT5zx3B3bg+w=; b=ZqH+66lvZKgCv7fJgWCnsvnwnQBRCWl+XguraSYuJUti0FDB8mteFRtDY7SJjsYeG8 n1M8WV+CVWPgloxSiF+f4tlkKKHkCO+suSlT+gMKY+neyybqte9ciGJEKbMY45Qm2sXS IPC4cJvwdD8T+lGAxKeGuzwWhwAeagbro0raE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yWHX9Q4LJTGZZowk5cb3ZATvK5oUhAswT5zx3B3bg+w=; b=KgvUMOwieohhMaFJxzFS0cPfpq9GO/Ljsg4/JPMB4G+W1zlVpbYPOqjul50VTA6idH tLJXkrnz7aK/TtybXbFI1G6IgrNQWDvxURvC77f4zbFe8Y4+nx3WDUCTxdISTvcrhuiA LZvubrUJW7Jrv4R9qMirCtu1z/wFHCd0IsH1HAl4C9fexhLEP0giVKapRR/3aw/nOHTG 9i/2v114jR+75QEz1S6sL3eHdPLKcSoUAC6sm5J3kOEY7ZqactMZUeRjCvF+P+Kv1yln fM2WoCNkwu3lmqXMRVqKJxBGnSWhn4ElamG68f7IEXAhGMkTODWdxuCArRaeMa9gw7Pr w5pQ== X-Gm-Message-State: APt69E0GXePRdZmMjRrLKgC7tGZJgzSXahOiCOMAIbjVqFImDMn7Jayb oou+iC3XSXAYyb2fyLABUd5k/A== X-Google-Smtp-Source: ADUXVKLcFy+2XNtrCEOHg2hi7kDghAesZLhOAgWzkBgREAL4Qo7qcKBvs29/su7SgiWWCkfDn3dzHA== X-Received: by 2002:a25:8891:: with SMTP id d17-v6mr6661981ybl.249.1529527728233; Wed, 20 Jun 2018 13:48:48 -0700 (PDT) Received: from rosewood.cam.corp.google.com ([2620:0:1013:11:ad55:b1db:adfe:3b9f]) by smtp.gmail.com with ESMTPSA id p3-v6sm1173865ywh.36.2018.06.20.13.48.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Jun 2018 13:48:47 -0700 (PDT) From: Sean Paul To: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Cc: robdclark@gmail.com, hoegsberg@chromium.org, jsanka@codeaurora.org, abhinavk@codeaurora.org, Sean Paul Subject: [DPU PATCH 06/19] drm/msm: dpu_encoder_phys_cmd: Replace DPU_EVT with tracepoints Date: Wed, 20 Jun 2018 16:48:28 -0400 Message-Id: <20180620204841.56354-7-seanpaul@chromium.org> X-Mailer: git-send-email 2.18.0.rc1.244.gcf134e6275-goog In-Reply-To: <20180620204841.56354-1-seanpaul@chromium.org> References: <20180620204841.56354-1-seanpaul@chromium.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch converts all DPU_EVTs in dpu_encoder_phys_cmd with either a DRM_* log message or a linux tracepoint. Signed-off-by: Sean Paul Reviewed-by: Rajesh Yadav --- .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 79 +++++++++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 68 ++++++++++++++++ 2 files changed, 104 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 388de384e2cf..eb9314aaa85f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -108,8 +108,9 @@ static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx) new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); - DPU_EVT32_IRQ(DRMID(phys_enc->parent), - phys_enc->hw_pp->idx - PINGPONG_0, new_cnt, event); + trace_dpu_enc_phys_cmd_pp_tx_done(DRMID(phys_enc->parent), + phys_enc->hw_pp->idx - PINGPONG_0, + new_cnt, event); /* Signal any waiting atomic commit thread */ wake_up_all(&phys_enc->pending_kickoff_wq); @@ -245,21 +246,20 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( do_log = true; } - DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0, - cmd_enc->pp_timeout_report_cnt, - atomic_read(&phys_enc->pending_kickoff_cnt), - frame_event); + trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(phys_enc->parent), + phys_enc->hw_pp->idx - PINGPONG_0, + cmd_enc->pp_timeout_report_cnt, + atomic_read(&phys_enc->pending_kickoff_cnt), + frame_event); /* to avoid flooding, only log first time, and "dead" time */ if (do_log) { - DPU_ERROR_CMDENC(cmd_enc, - "pp:%d kickoff timed out ctl %d cnt %d koff_cnt %d\n", - phys_enc->hw_pp->idx - PINGPONG_0, - phys_enc->hw_ctl->idx - CTL_0, - cmd_enc->pp_timeout_report_cnt, - atomic_read(&phys_enc->pending_kickoff_cnt)); - - DPU_EVT32(DRMID(phys_enc->parent), DPU_EVTLOG_FATAL); + DRM_ERROR("id:%d pp:%d kickoff timeout %d cnt %d koff_cnt %d\n", + DRMID(phys_enc->parent), + phys_enc->hw_pp->idx - PINGPONG_0, + phys_enc->hw_ctl->idx - CTL_0, + cmd_enc->pp_timeout_report_cnt, + atomic_read(&phys_enc->pending_kickoff_cnt)); dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR); DPU_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus", "panic"); @@ -308,8 +308,6 @@ static int dpu_encoder_phys_cmd_control_vblank_irq( struct dpu_encoder_phys *phys_enc, bool enable) { - struct dpu_encoder_phys_cmd *cmd_enc = - to_dpu_encoder_phys_cmd(phys_enc); int ret = 0; int refcount; @@ -330,10 +328,9 @@ static int dpu_encoder_phys_cmd_control_vblank_irq( goto end; } - DPU_DEBUG_CMDENC(cmd_enc, "[%pS] enable=%d/%d\n", - __builtin_return_address(0), enable, refcount); - DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0, - enable, refcount); + DRM_DEBUG_KMS("id:%u pp:%d enable=%s/%d\n", DRMID(phys_enc->parent), + phys_enc->hw_pp->idx - PINGPONG_0, + enable ? "true" : "false", refcount); if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1) ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_RDPTR); @@ -343,12 +340,10 @@ static int dpu_encoder_phys_cmd_control_vblank_irq( end: if (ret) { - DPU_ERROR_CMDENC(cmd_enc, - "control vblank irq error %d, enable %d, refcount %d\n", - ret, enable, refcount); - DPU_EVT32(DRMID(phys_enc->parent), - phys_enc->hw_pp->idx - PINGPONG_0, - enable, refcount, DPU_EVTLOG_ERROR); + DRM_ERROR("vblank irq err id:%u pp:%d ret:%d, enable %s/%d\n", + DRMID(phys_enc->parent), + phys_enc->hw_pp->idx - PINGPONG_0, ret, + enable ? "true" : "false", refcount); } return ret; @@ -364,7 +359,8 @@ void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc, cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); - DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0, + trace_dpu_enc_phys_cmd_irq_ctrl(DRMID(phys_enc->parent), + phys_enc->hw_pp->idx - PINGPONG_0, enable, atomic_read(&phys_enc->vblank_refcount)); if (enable) { @@ -557,7 +553,7 @@ static void _dpu_encoder_phys_cmd_connect_te( !phys_enc->hw_pp->ops.connect_external_te) return; - DPU_EVT32(DRMID(phys_enc->parent), enable); + trace_dpu_enc_phys_cmd_connect_te(DRMID(phys_enc->parent), enable); phys_enc->hw_pp->ops.connect_external_te(phys_enc->hw_pp, enable); } @@ -594,11 +590,9 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) DPU_ERROR("invalid encoder\n"); return; } - DPU_DEBUG_CMDENC(cmd_enc, "pp %d state %d\n", - phys_enc->hw_pp->idx - PINGPONG_0, - phys_enc->enable_state); - DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0, - phys_enc->enable_state); + DRM_DEBUG_KMS("id:%u pp:%d state:%d\n", DRMID(phys_enc->parent), + phys_enc->hw_pp->idx - PINGPONG_0, + phys_enc->enable_state); if (phys_enc->enable_state == DPU_ENC_DISABLED) { DPU_ERROR_CMDENC(cmd_enc, "already disabled\n"); @@ -656,10 +650,9 @@ static void dpu_encoder_phys_cmd_prepare_for_kickoff( DPU_ERROR("invalid encoder\n"); return; } - DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0); - - DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0, - atomic_read(&phys_enc->pending_kickoff_cnt)); + DRM_DEBUG_KMS("id:%u pp:%d pending_cnt:%d\n", DRMID(phys_enc->parent), + phys_enc->hw_pp->idx - PINGPONG_0, + atomic_read(&phys_enc->pending_kickoff_cnt)); /* * Mark kickoff request as outstanding. If there are more than one, @@ -669,9 +662,9 @@ static void dpu_encoder_phys_cmd_prepare_for_kickoff( if (ret) { /* force pending_kickoff_cnt 0 to discard failed kickoff */ atomic_set(&phys_enc->pending_kickoff_cnt, 0); - DPU_EVT32(DRMID(phys_enc->parent), - phys_enc->hw_pp->idx - PINGPONG_0); - DPU_ERROR("failed wait_for_idle: %d\n", ret); + DRM_ERROR("failed wait_for_idle: id:%u ret:%d pp:%d\n", + DRMID(phys_enc->parent), ret, + phys_enc->hw_pp->idx - PINGPONG_0); } DPU_DEBUG_CMDENC(cmd_enc, "pp:%d pending_cnt %d\n", @@ -720,9 +713,9 @@ static int dpu_encoder_phys_cmd_wait_for_tx_complete( rc = _dpu_encoder_phys_cmd_wait_for_idle(phys_enc); if (rc) { - DPU_EVT32(DRMID(phys_enc->parent), - phys_enc->intf_idx - INTF_0); - DPU_ERROR("failed wait_for_idle: %d\n", rc); + DRM_ERROR("failed wait_for_idle: id:%u ret:%d intf:%d\n", + DRMID(phys_enc->parent), rc, + phys_enc->intf_idx - INTF_0); } return rc; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index 7169ff3a9805..a6313c4343c8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -437,6 +437,10 @@ DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_frame_event_cb, TP_PROTO(uint32_t drm_id, bool enable), TP_ARGS(drm_id, enable) ); +DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_phys_cmd_connect_te, + TP_PROTO(uint32_t drm_id, bool enable), + TP_ARGS(drm_id, enable) +); TRACE_EVENT(dpu_enc_rc, TP_PROTO(uint32_t drm_id, u32 sw_event, bool idle_pc_supported, @@ -604,6 +608,70 @@ TRACE_EVENT(dpu_enc_wait_event_timeout, __entry->expected_time, __entry->atomic_cnt) ); +TRACE_EVENT(dpu_enc_phys_cmd_irq_ctrl, + TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, bool enable, + int refcnt), + TP_ARGS(drm_id, pp, enable, refcnt), + TP_STRUCT__entry( + __field( uint32_t, drm_id ) + __field( enum dpu_pingpong, pp ) + __field( bool, enable ) + __field( int, refcnt ) + ), + TP_fast_assign( + __entry->drm_id = drm_id; + __entry->pp = pp; + __entry->enable = enable; + __entry->refcnt = refcnt; + ), + TP_printk("id=%u, pp=%d, enable=%s, refcnt=%d", __entry->drm_id, + __entry->pp, __entry->enable ? "true" : "false", + __entry->refcnt) +); + +TRACE_EVENT(dpu_enc_phys_cmd_pp_tx_done, + TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int new_count, + u32 event), + TP_ARGS(drm_id, pp, new_count, event), + TP_STRUCT__entry( + __field( uint32_t, drm_id ) + __field( enum dpu_pingpong, pp ) + __field( int, new_count ) + __field( u32, event ) + ), + TP_fast_assign( + __entry->drm_id = drm_id; + __entry->pp = pp; + __entry->new_count = new_count; + __entry->event = event; + ), + TP_printk("id=%u, pp=%d, new_count=%d, event=%u", __entry->drm_id, + __entry->pp, __entry->new_count, __entry->event) +); + +TRACE_EVENT(dpu_enc_phys_cmd_pdone_timeout, + TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int timeout_count, + int kickoff_count, u32 event), + TP_ARGS(drm_id, pp, timeout_count, kickoff_count, event), + TP_STRUCT__entry( + __field( uint32_t, drm_id ) + __field( enum dpu_pingpong, pp ) + __field( int, timeout_count ) + __field( int, kickoff_count ) + __field( u32, event ) + ), + TP_fast_assign( + __entry->drm_id = drm_id; + __entry->pp = pp; + __entry->timeout_count = timeout_count; + __entry->kickoff_count = kickoff_count; + __entry->event = event; + ), + TP_printk("id=%u, pp=%d, timeout_count=%d, kickoff_count=%d, event=%u", + __entry->drm_id, __entry->pp, __entry->timeout_count, + __entry->kickoff_count, __entry->event) +); + TRACE_EVENT(dpu_crtc_setup_mixer, TP_PROTO(uint32_t crtc_id, uint32_t plane_id, struct drm_plane_state *state, struct dpu_plane_state *pstate,