From patchwork Wed Jun 20 20:48:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Paul X-Patchwork-Id: 10478697 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5FB3560383 for ; Wed, 20 Jun 2018 20:48:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 51D0428390 for ; Wed, 20 Jun 2018 20:48:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 46B07283AF; Wed, 20 Jun 2018 20:48:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C6AC128390 for ; Wed, 20 Jun 2018 20:48:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933154AbeFTUsu (ORCPT ); Wed, 20 Jun 2018 16:48:50 -0400 Received: from mail-yb0-f180.google.com ([209.85.213.180]:37106 "EHLO mail-yb0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933217AbeFTUst (ORCPT ); Wed, 20 Jun 2018 16:48:49 -0400 Received: by mail-yb0-f180.google.com with SMTP id h141-v6so363764ybg.4 for ; Wed, 20 Jun 2018 13:48:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OD51nDEEh863SLAveLEfRxwXxRbwZNyA4ESx/WB54uw=; b=jNTlnvsx9wBZTyC2u1E4Pl1Uh0wECdQutNenygo6S2EHPRxCJWgea6IgSVnokNx5Ck go1GC4T9rfBz/Zq62+XjWB4kiJmY0b9vXQSLHSvhnhh8g+te7NLyRFyBf9MyGpMvKBhz 7UrXToNL3kSn8KDFbC/8yhDpT/kSQX7T8+AbQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OD51nDEEh863SLAveLEfRxwXxRbwZNyA4ESx/WB54uw=; b=tMEudwdhblb9mhYZ3YDabocTRNqtAHOwvxBWpsj+/KayIZyRACREnv1skUY3wmh2DR Mh4q++MmUcg81KC0R2620SHPfDJtYES2AtvknSqrfT++7Bf9yOWA6Hp4JLRMLbADX5x8 bHG9Cg5DWROV/jsAvQ+yaljH8KJKEKdrbEj+93R0wkL3z/7i5gMWHqBOAxk8SjXk8Ebt w8fi+G6MafYoHA1wINSmDoO2oBDyOs1TYMrp17bZeZFJwS5TeLGoAVtW4rFXhSQKtm6A SMNl2xlfb85V1uAREenmskEiuX3JjRGdLFWsZmPCaVmIQ7oGyG1XbROEj6UWOMXOIb9F 0XOg== X-Gm-Message-State: APt69E10WMu/aD+m2sOYgTiRe0MXpwm6sSDqwOnhRzN8blzIBneIuDeV 3LmicV+Bac3IfLD2cEW6/rcLOXILywc= X-Google-Smtp-Source: ADUXVKK6eluvFKphBJN7R/g6ZgRtGu2rr+0sDHu8qHQJDSSWRO+MaFQmH4Jo1UIrl7upxP/GbelU7g== X-Received: by 2002:a25:d10c:: with SMTP id i12-v6mr11139504ybg.183.1529527728929; Wed, 20 Jun 2018 13:48:48 -0700 (PDT) Received: from rosewood.cam.corp.google.com ([2620:0:1013:11:ad55:b1db:adfe:3b9f]) by smtp.gmail.com with ESMTPSA id p3-v6sm1173865ywh.36.2018.06.20.13.48.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Jun 2018 13:48:48 -0700 (PDT) From: Sean Paul To: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Cc: robdclark@gmail.com, hoegsberg@chromium.org, jsanka@codeaurora.org, abhinavk@codeaurora.org, Sean Paul Subject: [DPU PATCH 07/19] drm/msm: dpu_encoder_phys_vid: Replace DPU_EVT with tracepoints Date: Wed, 20 Jun 2018 16:48:29 -0400 Message-Id: <20180620204841.56354-8-seanpaul@chromium.org> X-Mailer: git-send-email 2.18.0.rc1.244.gcf134e6275-goog In-Reply-To: <20180620204841.56354-1-seanpaul@chromium.org> References: <20180620204841.56354-1-seanpaul@chromium.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch converts all DPU_EVTs in dpu_encoder_phys_vid with either a DRM_* log message or a linux tracepoint. Signed-off-by: Sean Paul Reviewed-by: Rajesh Yadav --- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 36 ++++++++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 35 ++++++++++++++++++ 2 files changed, 50 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 73e59382eeac..fc83745b48fa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -458,12 +458,8 @@ static int dpu_encoder_phys_vid_control_vblank_irq( goto end; } - DPU_DEBUG_VIDENC(vid_enc, "[%pS] enable=%d/%d\n", - __builtin_return_address(0), - enable, atomic_read(&phys_enc->vblank_refcount)); - - DPU_EVT32(DRMID(phys_enc->parent), enable, - atomic_read(&phys_enc->vblank_refcount)); + DRM_DEBUG_KMS("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable, + atomic_read(&phys_enc->vblank_refcount)); if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1) ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_VSYNC); @@ -473,12 +469,10 @@ static int dpu_encoder_phys_vid_control_vblank_irq( end: if (ret) { - DPU_ERROR_VIDENC(vid_enc, - "control vblank irq error %d, enable %d\n", - ret, enable); - DPU_EVT32(DRMID(phys_enc->parent), - vid_enc->hw_intf->idx - INTF_0, - enable, refcount, DPU_EVTLOG_ERROR); + DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n", + DRMID(phys_enc->parent), + vid_enc->hw_intf->idx - INTF_0, ret, enable, + refcount); } return ret; } @@ -697,11 +691,9 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) ret = _dpu_encoder_phys_vid_wait_for_vblank(phys_enc, false); if (ret) { atomic_set(&phys_enc->pending_kickoff_cnt, 0); - DPU_ERROR_VIDENC(vid_enc, - "failure waiting for disable: %d\n", - ret); - DPU_EVT32(DRMID(phys_enc->parent), - vid_enc->hw_intf->idx - INTF_0, ret); + DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n", + DRMID(phys_enc->parent), + vid_enc->hw_intf->idx - INTF_0, ret); } } @@ -727,8 +719,8 @@ static void dpu_encoder_phys_vid_handle_post_kickoff( * Video encoders need to turn on their interfaces now */ if (phys_enc->enable_state == DPU_ENC_ENABLING) { - DPU_EVT32(DRMID(phys_enc->parent), - vid_enc->hw_intf->idx - INTF_0); + trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent), + vid_enc->hw_intf->idx - INTF_0); spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); vid_enc->hw_intf->ops.enable_timing(vid_enc->hw_intf, 1); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); @@ -747,8 +739,10 @@ static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc, vid_enc = to_dpu_encoder_phys_vid(phys_enc); - DPU_EVT32(DRMID(phys_enc->parent), vid_enc->hw_intf->idx - INTF_0, - enable, atomic_read(&phys_enc->vblank_refcount)); + trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent), + vid_enc->hw_intf->idx - INTF_0, + enable, + atomic_read(&phys_enc->vblank_refcount)); if (enable) { ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index a6313c4343c8..c9041e2a7aa1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -672,6 +672,41 @@ TRACE_EVENT(dpu_enc_phys_cmd_pdone_timeout, __entry->kickoff_count, __entry->event) ); +TRACE_EVENT(dpu_enc_phys_vid_post_kickoff, + TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx), + TP_ARGS(drm_id, intf_idx), + TP_STRUCT__entry( + __field( uint32_t, drm_id ) + __field( enum dpu_intf, intf_idx ) + ), + TP_fast_assign( + __entry->drm_id = drm_id; + __entry->intf_idx = intf_idx; + ), + TP_printk("id=%u, intf_idx=%d", __entry->drm_id, __entry->intf_idx) +); + +TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl, + TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, bool enable, + int refcnt), + TP_ARGS(drm_id, intf_idx, enable, refcnt), + TP_STRUCT__entry( + __field( uint32_t, drm_id ) + __field( enum dpu_intf, intf_idx ) + __field( bool, enable ) + __field( int, refcnt ) + ), + TP_fast_assign( + __entry->drm_id = drm_id; + __entry->intf_idx = intf_idx; + __entry->enable = enable; + __entry->refcnt = refcnt; + ), + TP_printk("id=%u, intf_idx=%d enable=%s refcnt=%d", __entry->drm_id, + __entry->intf_idx, __entry->enable ? "true" : "false", + __entry->drm_id) +); + TRACE_EVENT(dpu_crtc_setup_mixer, TP_PROTO(uint32_t crtc_id, uint32_t plane_id, struct drm_plane_state *state, struct dpu_plane_state *pstate,