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bh=MuQ4soFXn6WpxqlAdwkaulXLsozcy5WO5ZaH4GKP+1M=; b=UCi6pbMHrfFK0Y23VJV46Izd/yOk1RFk+HKLvOCz3jWmbn2ZppLd0ayVhBNgdBcrDb wEFig2YtwqqXvPPYPZ9a/52VgQ55cXCHMLoprtpusu3xZPfKXNh+2so4F6aWUkT9R4+J cUew68k/q0cqQEwlmZIwd3eBUTJsCdlxlWefgNDcyyzLHdVcpx/2jU9GWuEydU/ysAeC fRcvVyrtxrPVqHA5jkFHdFG0+ifulirHit3k2C4dYXS8B26HtNWb0SBluO7vSpynsRp/ GHLlSC11fnWw4QBfpNCMLLc+3ldjFNQ3cZgUeQPW99s7Zwl21EfSW0S/bRtVI9DaN3nF LT1g== X-Gm-Message-State: APt69E0plbStK0Dd1qxNGTX7l4kbz2iLb0zDdp55YWgcdb1iVgI7hlgU OFlK6KxJ/0rBncn7cJ4JamaXzw== X-Google-Smtp-Source: AAOMgpcidUuJK3Yl8jDwsqbjzBdiK6lnrmyKf8nvHdFZEIAvTmLua5DfGNmVG1zBcuWFoHxzVGw4vg== X-Received: by 2002:a81:4b57:: with SMTP id y84-v6mr5842810ywa.35.1530219219134; Thu, 28 Jun 2018 13:53:39 -0700 (PDT) Received: from rosewood.cam.corp.google.com ([2620:0:1013:11:ad55:b1db:adfe:3b9f]) by smtp.gmail.com with ESMTPSA id 199-v6sm2982681ywh.95.2018.06.28.13.53.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Jun 2018 13:53:38 -0700 (PDT) From: Sean Paul To: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Cc: robdclark@gmail.com, hoegsberg@chromium.org, jsanka@codeaurora.org, abhinavk@codeaurora.org, Sean Paul Subject: [DPU PATCH 5/6] drm/msm: Fix dpu compile when CONFIG_DEBUG_FS !defined Date: Thu, 28 Jun 2018 16:53:33 -0400 Message-Id: <20180628205334.158846-6-seanpaul@chromium.org> X-Mailer: git-send-email 2.18.0.399.gad0ab374a1-goog In-Reply-To: <20180628205334.158846-1-seanpaul@chromium.org> References: <20180628205334.158846-1-seanpaul@chromium.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/Makefile | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 3624b5af5ecd..1639ea8c0d13 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -49,7 +49,6 @@ msm-y := \ disp/dpu1/dpu_core_irq.o \ disp/dpu1/dpu_core_perf.o \ disp/dpu1/dpu_crtc.o \ - disp/dpu1/dpu_dbg.o \ disp/dpu1/dpu_encoder.o \ disp/dpu1/dpu_encoder_phys_cmd.o \ disp/dpu1/dpu_encoder_phys_vid.o \ @@ -92,7 +91,8 @@ msm-y := \ msm_ringbuffer.o \ msm_submitqueue.o -msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o +msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \ + disp/dpu1/dpu_dbg.o msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o msm-$(CONFIG_COMMON_CLK) += disp/mdp4/mdp4_lvds_pll.o diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h index 05504e676f6a..89edf2526aca 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h @@ -98,11 +98,11 @@ static inline void dpu_dbg_destroy(void) } static inline void dpu_dbg_dump(bool queue_work, const char *name, - bool dump_dbgbus_dpu, bool dump_dbgbus_vbif_rt); + bool dump_dbgbus_dpu, bool dump_dbgbus_vbif_rt) { } -void dpu_dbg_set_dpu_top_offset(u32 blk_off) +static inline void dpu_dbg_set_dpu_top_offset(u32 blk_off) { }