From patchwork Mon Jul 9 17:31:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Paul X-Patchwork-Id: 10515329 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 36D9C6032A for ; Mon, 9 Jul 2018 17:32:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1B15A28DC4 for ; Mon, 9 Jul 2018 17:32:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0F44428DD2; Mon, 9 Jul 2018 17:32:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B8BB428DCC for ; Mon, 9 Jul 2018 17:32:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933573AbeGIRcf (ORCPT ); Mon, 9 Jul 2018 13:32:35 -0400 Received: from mail-yb0-f196.google.com ([209.85.213.196]:34032 "EHLO mail-yb0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933593AbeGIRce (ORCPT ); Mon, 9 Jul 2018 13:32:34 -0400 Received: by mail-yb0-f196.google.com with SMTP id e9-v6so7498853ybq.1 for ; Mon, 09 Jul 2018 10:32:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OSA0lNCWmvWc26uO1rhD8YsZGG7yFrdA4Zp/aDYlCnI=; b=KeIwiF91ADikYdnn4teixJEZjPx4dj4CiU6YS2PAVfTfzR9hDMYi36lw5+jHLNdzBN hUVvA6mRv0Hiuq1ocylkgH/ZLywjMkzT4WqHIKTLT2yJyKkEAUKSPJKIyr8ngUYDFtDG vrBqjzBNtP+z4Ufj1VnF/BmmK8Xulb3DZ9Mn4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OSA0lNCWmvWc26uO1rhD8YsZGG7yFrdA4Zp/aDYlCnI=; b=ALR+gn+v6gi7eBBoivmwoWvKeSgkoIr7dvmXGG8qQYOIa0AIuKz1UsZJugZNEdUBPb KL5CLF2z+hTg3KkOl+Dz/MEs4JLJs7siNewY+rxTiuBM47rq75ed4KXVVX90Z9NFeuui 4jzNB6nFRl51ARb7edpukX8W2UlWaWfh4vntxvTfse7Fdj3QzX6OpD3qG8wlyxU4X1Na uGHJtTT0pC7mkw0p+G73KmrYcVtXx0Jr961bw5i54037lKXm4VvS33gW4L65VFbH0G/S Lkym7IT6YLsigvBBjvMoYg8TOk8Dd6cq7mu35d8n7aFtYsaAnVY0HtioKW9a3FZ3Hv4N +hJA== X-Gm-Message-State: APt69E0w+BKNCXIb/cwvMRwdSMB7b9OYFvdSkh/nqpf6xsacrb5+Lji2 x4C0NnkkM1kNJGI+DQHW/MqD+g== X-Google-Smtp-Source: AAOMgpdXG7h+iDvBEw+vcdHDX/WY6UI5Y2ONQEe2lN/weH0qGHD+UQUzNZ4lRFSBWD4+2c6WIPgaHw== X-Received: by 2002:a25:8581:: with SMTP id x1-v6mr11351743ybk.233.1531157553472; Mon, 09 Jul 2018 10:32:33 -0700 (PDT) Received: from rosewood.cam.corp.google.com ([2620:0:1013:11:ad55:b1db:adfe:3b9f]) by smtp.gmail.com with ESMTPSA id s206-v6sm5885495ywc.55.2018.07.09.10.32.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Jul 2018 10:32:32 -0700 (PDT) From: Sean Paul To: abhinavk@codeaurora.org, architt@codeaurora.org, chandanu@codeaurora.org, jsanka@codeaurora.org, jcrouse@codeaurora.org, ryadav@codeaurora.org, seanpaul@chromium.org, skolluku@codeaurora.org, dri-devel@lists.freedesktop.org, robdclark@gmail.com, airlied@linux.ie, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, nganji@codeaurora.org, hoegsberg@chromium.org, dovizu@chromium.org, robh+dt@kernel.org Cc: Taniya Das , Michael Turquette , Stephen Boyd , Mark Rutland , linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 02/21] dt-bindings: clock: Introduce QCOM Display clock bindings Date: Mon, 9 Jul 2018 13:31:38 -0400 Message-Id: <20180709173200.238457-3-seanpaul@chromium.org> X-Mailer: git-send-email 2.18.0.203.gfac676dfb9-goog In-Reply-To: <20180709173200.238457-1-seanpaul@chromium.org> References: <20180709173200.238457-1-seanpaul@chromium.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Taniya Das Add device tree bindings for display clock controller for Qualcomm Technology Inc's SDM845 SoCs. Signed-off-by: Taniya Das Reviewed-by: Rob Herring Signed-off-by: Sean Paul --- .../devicetree/bindings/clock/qcom,dispcc.txt | 19 ++++++++ .../dt-bindings/clock/qcom,dispcc-sdm845.h | 45 +++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc.txt create mode 100644 include/dt-bindings/clock/qcom,dispcc-sdm845.h diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt new file mode 100644 index 000000000000..d639e18d0b85 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt @@ -0,0 +1,19 @@ +Qualcomm Technologies, Inc. Display Clock Controller Binding +------------------------------------------------------------ + +Required properties : + +- compatible : shall contain "qcom,sdm845-dispcc" +- reg : shall contain base register location and length. +- #clock-cells : from common clock binding, shall contain 1. +- #reset-cells : from common reset binding, shall contain 1. +- #power-domain-cells : from generic power domain binding, shall contain 1. + +Example: + dispcc: clock-controller@af00000 { + compatible = "qcom,sdm845-dispcc"; + reg = <0xaf00000 0x100000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h new file mode 100644 index 000000000000..11eed4bc9646 --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sdm845.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H +#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H + +/* DISP_CC clock registers */ +#define DISP_CC_MDSS_AHB_CLK 0 +#define DISP_CC_MDSS_AXI_CLK 1 +#define DISP_CC_MDSS_BYTE0_CLK 2 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 4 +#define DISP_CC_MDSS_BYTE1_CLK 5 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 6 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 7 +#define DISP_CC_MDSS_ESC0_CLK 8 +#define DISP_CC_MDSS_ESC0_CLK_SRC 9 +#define DISP_CC_MDSS_ESC1_CLK 10 +#define DISP_CC_MDSS_ESC1_CLK_SRC 11 +#define DISP_CC_MDSS_MDP_CLK 12 +#define DISP_CC_MDSS_MDP_CLK_SRC 13 +#define DISP_CC_MDSS_MDP_LUT_CLK 14 +#define DISP_CC_MDSS_PCLK0_CLK 15 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 16 +#define DISP_CC_MDSS_PCLK1_CLK 17 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 18 +#define DISP_CC_MDSS_ROT_CLK 19 +#define DISP_CC_MDSS_ROT_CLK_SRC 20 +#define DISP_CC_MDSS_RSCC_AHB_CLK 21 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22 +#define DISP_CC_MDSS_VSYNC_CLK 23 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 24 +#define DISP_CC_PLL0 25 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27 + +/* DISP_CC Reset */ +#define DISP_CC_MDSS_RSCC_BCR 0 + +/* DISP_CC GDSCR */ +#define MDSS_GDSC 0 + +#endif