From patchwork Thu Jul 12 18:59:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10522175 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 351F76032C for ; Thu, 12 Jul 2018 18:59:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2232C29CDC for ; Thu, 12 Jul 2018 18:59:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 167E929CE4; Thu, 12 Jul 2018 18:59:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 79E7429CDC for ; Thu, 12 Jul 2018 18:59:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726634AbeGLTKi (ORCPT ); Thu, 12 Jul 2018 15:10:38 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:47382 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726798AbeGLTKi (ORCPT ); Thu, 12 Jul 2018 15:10:38 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E7D4C60B74; Thu, 12 Jul 2018 18:59:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1531421988; bh=nEJ3DXYb6yllr0KmCpzno6J54+pB4qbOaTLryinFUBM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=flq2Tih6uui1RPJvc4l8F6JlUl4SIJQLuocALQPAJikbHR9KevED4B47HTDdY2aKn B/NRMQ8nWn1++bQQGTcrryg248foKUZxaBuDjcfLsOMdyRiMPaziz2HxJvu20sjI3/ KmZ+uUMzJorcK4Blh+azjUPLPUFNEKNBaIlyMwvU= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1124860BE9; Thu, 12 Jul 2018 18:59:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1531421981; bh=nEJ3DXYb6yllr0KmCpzno6J54+pB4qbOaTLryinFUBM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bbIOxZj6jM0sH/q+0oRwVyu+IVyvT8bCixh7vJ5bwGAou2Pzo8sw7A2jJDBpsYNVn 3vu8MGflHesTcifMpmj0EedJYDjKg0/TMiqrtaXmZv5i8jXwiqTldlB86jU+2ypaG0 2ZESU47tB4D7N94w2lquNS6bna1kNfdPjtpLMREc= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1124860BE9 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 11/13] drm/msm/adreno: Add ringbuffer data to the GPU state Date: Thu, 12 Jul 2018 12:59:28 -0600 Message-Id: <20180712185930.2492-12-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180712185930.2492-1-jcrouse@codeaurora.org> References: <20180712185930.2492-1-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the contents of each ringbuffer to the GPU state and dump the data in the crash file encoded with ascii85. To save space only the used portions of the ringbuffer are dumped. Signed-off-by: Jordan Crouse --- Documentation/gpu/drm-msm-crash-dump.txt | 5 +++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 41 ++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_gpu.h | 2 ++ 3 files changed, 48 insertions(+) diff --git a/Documentation/gpu/drm-msm-crash-dump.txt b/Documentation/gpu/drm-msm-crash-dump.txt index 930e4c970a62..7083075c6f87 100644 --- a/Documentation/gpu/drm-msm-crash-dump.txt +++ b/Documentation/gpu/drm-msm-crash-dump.txt @@ -35,6 +35,11 @@ bos: # List of buffers from the hanging submission (if known) # ascii85. Only the contents of buffers marked as # readable are dumped. Trailing zeros at the end of the # buffer won't be dumped. + size: # [decimal] The maximum size of the ring programmed in + # the hardware + data: # [ascii85] The contents of the ring encoded as ascii85. + # Only the unused portions of the ring will be printed + # (up to a maximum of 'size' bytes) registers: # Sets of register values. This section can be used multiple # times for different ranges of registers. Each register will be # on its own line. diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 15fe0d029ba6..92acce377253 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -17,6 +17,7 @@ * this program. If not, see . */ +#include #include #include "adreno_gpu.h" #include "msm_gem.h" @@ -383,10 +384,30 @@ struct msm_gpu_state *adreno_gpu_state_get(struct msm_gpu *gpu) do_gettimeofday(&state->time); for (i = 0; i < gpu->nr_rings; i++) { + int size = 0, j; + state->ring[i].fence = gpu->rb[i]->memptrs->fence; state->ring[i].seqno = gpu->rb[i]->seqno; state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]); state->ring[i].wptr = get_wptr(gpu->rb[i]); + + /* + * Only copy used parts of the ring buffers (this should save + * data size for lightly used rings) + */ + for (j = 0; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++) + if (gpu->rb[i]->start[j]) + size = j; + + if (size) { + state->ring[i].data = kmalloc((size + 1) << 2, + GFP_KERNEL); + if (state->ring[i].data) { + memcpy(state->ring[i].data, gpu->rb[i]->start, + (size + 1) << 2); + state->ring[i].data_size = (size + 1) << 2; + } + } } /* Count the number of registers */ @@ -417,9 +438,13 @@ struct msm_gpu_state *adreno_gpu_state_get(struct msm_gpu *gpu) static void adreno_gpu_state_destroy(struct kref *kref) { + int i; struct msm_gpu_state *state = container_of(kref, struct msm_gpu_state, ref); + for (i = 0; i < ARRAY_SIZE(state->ring); i++) + kfree(state->ring[i].data); + kfree(state->comm); kfree(state->cmd); kfree(state->registers); @@ -459,6 +484,22 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, drm_printf(p, " retired-fence: %d\n", state->ring[i].fence); drm_printf(p, " rptr: %d\n", state->ring[i].rptr); drm_printf(p, " wptr: %d\n", state->ring[i].wptr); + drm_printf(p, " size: %d\n", MSM_GPU_RINGBUFFER_SZ); + + if (state->ring[i].data && state->ring[i].data_size) { + u32 *ptr = (u32 *) state->ring[i].data; + char out[ASCII85_BUFSZ]; + long len = ascii85_encode_len(state->ring[i].data_size); + int j; + + drm_printf(p, " data: !!ascii85 |\n"); + drm_printf(p, " "); + + for (j = 0; j < len; j++) + drm_printf(p, ascii85_encode(ptr[j], out)); + + drm_printf(p, "\n"); + } } drm_puts(p, "registers:\n"); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index e65f507954c0..48f7b21f1cae 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -190,6 +190,8 @@ struct msm_gpu_state { u32 seqno; u32 rptr; u32 wptr; + void *data; + int data_size; } ring[MSM_GPU_MAX_RINGS]; int nr_registers;