From patchwork Thu Jul 12 21:13:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Paul X-Patchwork-Id: 10522329 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7EF8D6032C for ; Thu, 12 Jul 2018 21:13:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6E51A29BFF for ; Thu, 12 Jul 2018 21:13:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 626D229C02; Thu, 12 Jul 2018 21:13:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA74729BFF for ; Thu, 12 Jul 2018 21:13:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732844AbeGLVYe (ORCPT ); Thu, 12 Jul 2018 17:24:34 -0400 Received: from mail-yb0-f195.google.com ([209.85.213.195]:35501 "EHLO mail-yb0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732812AbeGLVYe (ORCPT ); Thu, 12 Jul 2018 17:24:34 -0400 Received: by mail-yb0-f195.google.com with SMTP id x15-v6so11965261ybm.2 for ; Thu, 12 Jul 2018 14:13:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Z30geUajURBJvwcdVqaKv9VQyJxGYmejsHzyUfXQa3E=; b=CD7PWQpV/yvRzAcIGIPdXy5ZfdrRYm9+lW0ixU+RCK2w12iScyYQ46bVqm2Y8q7g6/ WxQlM0uE7K2lxB/PsSb//suqic/yYM3eOmFYDfpK+MVQWy4ZWEwEjnzopEgaphsmJXHV 5YPr4eCfOS/grqD5UowhZkIV9mnyRxHEQNNTw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z30geUajURBJvwcdVqaKv9VQyJxGYmejsHzyUfXQa3E=; b=MgonBAMA8LCybbzj9LsUbKZCKSU1LZCaccRHfgGXJTCsv/YhAZJXkpqlhUO9dE8GuZ VzR2Sf68qrgbHXKHiLXOOUVkRGfIWQhjT/hFMRK7PInwPM51PhxINkL8FE4q+vqncOxk VYPdCaC3iphx677vi0T36MUkp2jEbjqvCQOimA/M/aFw+wgClvUDeFr6MF1W03WmPRDC 4BsFiodCPEOPoKz33P06qdEVUIdHFyWr1Bk/HOmjUSj4PgB1GuJ+rxU301I/2q9PBCJp 9jNy3svtCFlKmPjx4QiV1QMCdVVKb1ACjN4q8yYevsZyE5aPkWCcBAb1src/U1TaLiQn 19UA== X-Gm-Message-State: AOUpUlH6c+yaFl6J+5wzUji5uZKNBNCFUhXF7WWsPOD2+N9m8fJTJvx2 z0s9JgnKApmXnsBHBy3YNsqnwH5D0go= X-Google-Smtp-Source: AAOMgperfCOQVPNl4+L+1kO8RE8CEKSsS1I/zvYrnXWkjmOxxek/bM/WqzaG0bo/lSaOIwgCGXSWIw== X-Received: by 2002:a25:1683:: with SMTP id 125-v6mr2055832ybw.217.1531429992817; Thu, 12 Jul 2018 14:13:12 -0700 (PDT) Received: from rosewood.cam.corp.google.com ([2620:0:1013:11:ad55:b1db:adfe:3b9f]) by smtp.gmail.com with ESMTPSA id q131-v6sm29275708ywq.8.2018.07.12.14.13.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 12 Jul 2018 14:13:12 -0700 (PDT) From: Sean Paul To: abhinavk@codeaurora.org, architt@codeaurora.org, chandanu@codeaurora.org, jsanka@codeaurora.org, jcrouse@codeaurora.org, ryadav@codeaurora.org, seanpaul@chromium.org, skolluku@codeaurora.org, dri-devel@lists.freedesktop.org, robdclark@gmail.com, airlied@linux.ie, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, nganji@codeaurora.org, hoegsberg@chromium.org, robh+dt@kernel.org Cc: Andy Gross , David Brown , Mark Rutland , Catalin Marinas , Will Deacon , linux-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 21/21] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file Date: Thu, 12 Jul 2018 17:13:00 -0400 Message-Id: <20180712211311.147851-1-seanpaul@chromium.org> X-Mailer: git-send-email 2.18.0.203.gfac676dfb9-goog In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP DPU is short for the Display Processing Unit. It is the display controller on Qualcomm SDM845 chips. While the dts is pretty sparse for sdm845 atm, the only piece we're missing is the iommu. It's commented out for now, and should be uncommented once support is provided. Changes in v2: - Beefed up commit message - Use SoC specific compatibles for mdss and dpu - Use assigned-clocks to set initial clock frequency Signed-off-by: Sean Paul --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 200 +++++++++++++++++++++++++++ 1 file changed, 200 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index cdaabeb3c995..f1f4cdc9cb63 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5,6 +5,8 @@ * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +#include +#include #include / { @@ -221,6 +223,204 @@ #interrupt-cells = <2>; }; + mdss: mdss@ae00000 { + compatible = "qcom,sdm845-mdss"; + reg = <0xae00000 0x1000>; + reg-names = "mdss_phys"; + + power-domains = <&dispcc 0>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + /* iommus = <&apps_iommu 0>; */ + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp_phys", "vbif_phys"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <300000000>, + <19200000>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0xae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 0>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte_clk", + "byte_intf_clk", + "pixel_clk", + "core_clk", + "iface_clk", + "bus_clk"; + + phys = <&dsi0_phy>; + phy-names = "dsi-phy"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0xae94400 0x200>, + <0xae94a00 0x1e0>, + <0xae94600 0x280>; + reg-names = "dsi_phy", + "dsi_pll", + "dsi_phy_lane"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + }; + + dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0xae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5 0>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AXI_CLK>; + clock-names = "byte_clk", + "byte_intf_clk", + "pixel_clk", + "core_clk", + "iface_clk", + "bus_clk"; + + phys = <&dsi1_phy>; + phy-names = "dsi-phy"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@ae96400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0xae96400 0x200>, + <0xae96a00 0x10e>, + <0xae96600 0x280>; + reg-names = "dsi_phy", + "dsi_pll", + "dsi_phy_lane"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + }; + }; + + dispcc: qcom,dispcc@af00000 { + compatible = "qcom,sdm845-dispcc"; + reg = <0xaf00000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1100>,