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Fri, 20 Jul 2018 20:46:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728435AbeGTVgP (ORCPT ); Fri, 20 Jul 2018 17:36:15 -0400 Received: from mail-yw0-f196.google.com ([209.85.161.196]:43728 "EHLO mail-yw0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727633AbeGTVgP (ORCPT ); Fri, 20 Jul 2018 17:36:15 -0400 Received: by mail-yw0-f196.google.com with SMTP id l189-v6so4811472ywb.10 for ; Fri, 20 Jul 2018 13:46:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VyhWqLN/53fV00YorW1G9X+/H3cNwPiztihr2qyHjfQ=; b=cao9asEQBgFXhG/4rWc5MmZFgtpqHUgo7kcxVITQEZZUgztDHoV0x9+U0jCuhjKeGA uhJEkRdWDCyTynbuiKBWbDNNYDEI25z5aWKJJmCYhPftPy17WWJFjSnIxJ8hsZx4s4DA q4gPRpet5zEkimjTW4DwjLvSjgrEp25md0Yhg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VyhWqLN/53fV00YorW1G9X+/H3cNwPiztihr2qyHjfQ=; b=U9FHL+as2aTCZmt8jsjaBdwafsDJC5sgMvZnkBFE6DuA8NQ115fSslcPJqmcYlt4A1 wBHn6Bj6232p19O4lbMn4q2Z1tGzuHJIuhxtf63hVES2771sxp6cSqaOUYIQZxsQ26+o lMEcJUMiDSvqHPZXofZQi5qC0KmBpd3IYkJeA27aPFpvBxkWvzFKGSldejlIpLEFcCvc 351J+GtDTHv8Xuh2rN2uo9EpwupoAKCb+G1voC+sUisZ2pz91FC/gCTNPhr8ysQRJrlm oiFw2AjE5bs+pkmETb4StbRVOTPo6BKw2/EzHqHkLbO+yI80Nsep0FUAt0yq1gI9t7xK hFKg== X-Gm-Message-State: AOUpUlHPkouH8YBhIKrs/1CsM0Usn6PsRnifJJiL2htt5myxfdnq2P7F eAmfZEDxwPrPccCc0VGZeNax/A== X-Google-Smtp-Source: AAOMgpfPnhqgRtvws2KhjwIReVSb3vRV+NQwi8SsYSCxj1Bp+Cqd1+mWn+fu8AjRrjQzXKo1J53gHw== X-Received: by 2002:a81:8d46:: with SMTP id w6-v6mr1826802ywj.122.1532119577595; Fri, 20 Jul 2018 13:46:17 -0700 (PDT) Received: from rosewood.cam.corp.google.com ([2620:0:1013:11:ad55:b1db:adfe:3b9f]) by smtp.gmail.com with ESMTPSA id a2-v6sm2453831ywm.7.2018.07.20.13.46.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Jul 2018 13:46:17 -0700 (PDT) From: Sean Paul To: abhinavk@codeaurora.org, architt@codeaurora.org, chandanu@codeaurora.org, jsanka@codeaurora.org, jcrouse@codeaurora.org, ryadav@codeaurora.org, seanpaul@chromium.org, skolluku@codeaurora.org, dri-devel@lists.freedesktop.org, robdclark@gmail.com, airlied@linux.ie, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, nganji@codeaurora.org, hoegsberg@chromium.org, dovizu@chromium.org, robh+dt@kernel.org Cc: Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v3 18/19] dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU Date: Fri, 20 Jul 2018 16:43:09 -0400 Message-Id: <20180720204315.19054-19-seanpaul@chromium.org> X-Mailer: git-send-email 2.18.0.233.g985f88cf7e-goog In-Reply-To: <20180720204315.19054-1-seanpaul@chromium.org> References: <20180720204315.19054-1-seanpaul@chromium.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jeykumar Sankaran Adds bindings for Snapdragon 845 display processing unit Changes in v2: - Use SoC specific compatibles for mdss and dpu (Rob Herring) - Use assigned-clocks to set initial clock frequency (Rob Herring) Changes in v3 (all suggested by Rob Herring): - Rename mdss_phys to mdss - Correct description for clocks/assigned-clocks - Rename mdp_phys to mdp - Rename vbif_phys to vbif - Remove redundant interrupt-parent from mdss_mdp - Fully specify 'ranges' and use relative reg address in mdss_mdp Cc: Rob Herring Signed-off-by: Jeykumar Sankaran Signed-off-by: Rajesh Yadav Signed-off-by: Sean Paul Reviewed-by: Rob Herring --- .../devicetree/bindings/display/msm/dpu.txt | 131 ++++++++++++++++++ 1 file changed, 131 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu.txt diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt new file mode 100644 index 000000000000..ad2e8830324e --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt @@ -0,0 +1,131 @@ +Qualcomm Technologies, Inc. DPU KMS + +Description: + +Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates +sub-blocks like DPU display controller, DSI and DP interfaces etc. +The DPU display controller is found in SDM845 SoC. + +MDSS: +Required properties: +- compatible: "qcom,sdm845-mdss" +- reg: physical base address and length of contoller's registers. +- reg-names: register region names. The following region is required: + * "mdss" +- power-domains: a power domain consumer specifier according to + Documentation/devicetree/bindings/power/power_domain.txt +- clocks: list of clock specifiers for clocks needed by the device. +- clock-names: device clock names, must be in same order as clocks property. + The following clocks are required: + * "iface" + * "bus" + * "core" +- interrupts: interrupt signal from MDSS. +- interrupt-controller: identifies the node as an interrupt controller. +- #interrupt-cells: specifies the number of cells needed to encode an interrupt + source, should be 1. +- iommus: phandle of iommu device node. +- #address-cells: number of address cells for the MDSS children. Should be 1. +- #size-cells: Should be 1. +- ranges: parent bus address space is the same as the child bus address space. + +Optional properties: +- assigned-clocks: list of clock specifiers for clocks needing rate assignment +- assigned-clock-rates: list of clock frequencies sorted in the same order as + the assigned-clocks property. + +MDP: +Required properties: +- compatible: "qcom,sdm845-dpu" +- reg: physical base address and length of controller's registers. +- reg-names : register region names. The following region is required: + * "mdp" + * "vbif" +- clocks: list of clock specifiers for clocks needed by the device. +- clock-names: device clock names, must be in same order as clocks property. + The following clocks are required. + * "bus" + * "iface" + * "core" + * "vsync" +- interrupts: interrupt line from DPU to MDSS. +- ports: contains the list of output ports from DPU device. These ports connect + to interfaces that are external to the DPU hardware, such as DSI, DP etc. + + Each output port contains an endpoint that describes how it is connected to an + external interface. These are described by the standard properties documented + here: + Documentation/devicetree/bindings/graph.txt + Documentation/devicetree/bindings/media/video-interfaces.txt + + Port 0 -> DPU_INTF1 (DSI1) + Port 1 -> DPU_INTF2 (DSI2) + +Optional properties: +- assigned-clocks: list of clock specifiers for clocks needing rate assignment +- assigned-clock-rates: list of clock frequencies sorted in the same order as + the assigned-clocks property. + +Example: + + mdss: mdss@ae00000 { + compatible = "qcom,sdm845-mdss"; + reg = <0xae00000 0x1000>; + reg-names = "mdss"; + + power-domains = <&clock_dispcc 0>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_iommu 0>; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xae00000 0xb2008>; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, + <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, + <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <0 0 300000000 19200000>; + + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + };