From patchwork Wed Jul 25 20:34:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Paul X-Patchwork-Id: 10544651 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 363EA9093 for ; Wed, 25 Jul 2018 20:36:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 268862AB3D for ; Wed, 25 Jul 2018 20:36:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1AC422AB4D; Wed, 25 Jul 2018 20:36:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A16A32AB3D for ; Wed, 25 Jul 2018 20:36:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730535AbeGYVtd (ORCPT ); Wed, 25 Jul 2018 17:49:33 -0400 Received: from mail-yb0-f194.google.com ([209.85.213.194]:45307 "EHLO mail-yb0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730400AbeGYVtd (ORCPT ); Wed, 25 Jul 2018 17:49:33 -0400 Received: by mail-yb0-f194.google.com with SMTP id h127-v6so3505350ybg.12 for ; Wed, 25 Jul 2018 13:36:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fNeUTlJ4GhpcI96stLqkvrFGlBMidcc1UWinuiedkOM=; b=RBdZ0gAvAROj3CjRPl5DVFRlkX9Kr0cZlJMUWbYAB6iEN6xzqLrAnfi90ias66TGgw 4BozGFUvmEz4QkJgFBxfGoDDz9HbFqqueOg3S/SySrFWxshNI1vkFflgERpOnlrTF3Ki V4/wx4/Xq1iKkQ/M2tix7zitHc+VGlDLL6Zec= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fNeUTlJ4GhpcI96stLqkvrFGlBMidcc1UWinuiedkOM=; b=VwbsBxVu0iX6atL7xmH4+mSN2Pd8CdMEu8XXMo56pbg+gKD2ihYmKlTo7bQW6zkwot UzfQUZDVQA2Eruvn6ByXXSeDtmQ0KY9Gynzw0BLXfdvj9hYVT8gtO0AjFtZEEbYBpgZ0 klebk6CUjV0vkon732QAb24SL7xIf26awbij+fNq0o+SH3XDJQ1I/G8KgMPXv3FN908c yGVh2YvhDBBEKbTlxYWzApezsz/GEsC3tH+TwrDxW0WZMjj++D0XiO4vqM0Q3Y0D1HZF PVDg7yP/ZUcxdbgfguF0KN0xqQ7pzc5oRX05St0AbFZQHZkK+3bY5JSozkWWQTs/Txew CHpQ== X-Gm-Message-State: AOUpUlFLAMxeU2Fn/aH3lKMFrh1oZO9Hf45ZEOjY1zlTGg6mbYnEE+0+ fdTyGgOX2yuKgBtx5mLlMfLfew== X-Google-Smtp-Source: AAOMgpfVjnL+pED6r8ueR8oK+1+6VAYDKIVDDnesE4vDLzQPR3M1DqzI/bMoEevYJQCHRrYlns1+5A== X-Received: by 2002:a25:ddc1:: with SMTP id u184-v6mr11405709ybg.457.1532550972869; Wed, 25 Jul 2018 13:36:12 -0700 (PDT) Received: from rosewood.cam.corp.google.com ([2620:0:1013:11:ad55:b1db:adfe:3b9f]) by smtp.gmail.com with ESMTPSA id f137-v6sm14692568ywb.52.2018.07.25.13.36.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Jul 2018 13:36:12 -0700 (PDT) From: Sean Paul Cc: Sean Paul , Rob Clark , Sibi Sankar , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 3/3] drm/msm: dsi: Handle dual-channel for 6G as well Date: Wed, 25 Jul 2018 16:34:45 -0400 Message-Id: <20180725203529.164928-3-seanpaul@chromium.org> X-Mailer: git-send-email 2.18.0.233.g985f88cf7e-goog In-Reply-To: <20180725203529.164928-1-seanpaul@chromium.org> References: <20180725203529.164928-1-seanpaul@chromium.org> To: unlisted-recipients:; (no To-header on input) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This fixes up a collision between introducing dual-channel support and the dsi refactors. This patch applies the same dual-channel considerations and pclk calculations to both v2 and 6G, with a bit of abstracting for good measure. Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/dsi/dsi_host.c | 72 +++++++++++++++--------------- 1 file changed, 35 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 319501dcc083..96fb5f635314 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -664,11 +664,9 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) clk_disable_unprepare(msm_host->byte_clk); } -int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi) +static u32 dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi) { struct drm_display_mode *mode = msm_host->mode; - u8 lanes = msm_host->lanes; - u32 bpp = dsi_get_bpp(msm_host->format); u32 pclk_rate; pclk_rate = mode->clock * 1000; @@ -676,61 +674,61 @@ int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi) /* * For dual DSI mode, the current DRM mode has the complete width of the * panel. Since, the complete panel is driven by two DSI controllers, - * theclock rates have to be split between the two dsi controllers. + * the clock rates have to be split between the two dsi controllers. * Adjust the byte and pixel clock rates for each dsi host accordingly. */ if (is_dual_dsi) pclk_rate /= 2; - if (lanes > 0) { - msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes); - } else { + return pclk_rate; +} + +static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_dual_dsi) +{ + u8 lanes = msm_host->lanes; + u32 bpp = dsi_get_bpp(msm_host->format); + u32 pclk_rate = dsi_get_pclk_rate(msm_host, is_dual_dsi); + u64 pclk_bpp = (u64)pclk_rate * bpp; + + if (lanes == 0) { pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); - msm_host->byte_clk_rate = (pclk_rate * bpp) / 8; + lanes = 1; } - DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate); + do_div(pclk_bpp, (8 * lanes)); - msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); + msm_host->pixel_clk_rate = pclk_rate; + msm_host->byte_clk_rate = pclk_bpp; + + DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate, + msm_host->byte_clk_rate); + +} + +int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi) +{ + if (!msm_host->mode) { + pr_err("%s: mode not set\n", __func__); + return -EINVAL; + } + dsi_calc_pclk(msm_host, is_dual_dsi); + msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); return 0; } int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi) { - struct drm_display_mode *mode = msm_host->mode; - u8 lanes = msm_host->lanes; u32 bpp = dsi_get_bpp(msm_host->format); - u32 pclk_rate; u64 pclk_bpp; unsigned int esc_mhz, esc_div; unsigned long byte_mhz; - pclk_rate = mode->clock * 1000; - - /* - * For dual DSI mode, the current DRM mode has the complete width of the - * panel. Since, the complete panel is driven by two DSI controllers, - * theclock rates have to be split between the two dsi controllers. - * Adjust the byte and pixel clock rates for each dsi host accordingly. - */ - if (is_dual_dsi) - pclk_rate /= 2; - - pclk_bpp = pclk_rate * bpp; - if (lanes > 0) { - do_div(pclk_bpp, (8 * lanes)); - } else { - pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); - do_div(pclk_bpp, 8); - } - msm_host->pixel_clk_rate = pclk_rate; - msm_host->byte_clk_rate = pclk_bpp; - - DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate, - msm_host->byte_clk_rate); + dsi_calc_pclk(msm_host, is_dual_dsi); - msm_host->src_clk_rate = (pclk_rate * bpp) / 8; + pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_dual_dsi) * bpp; + do_div(pclk_bpp, 8); + msm_host->src_clk_rate = pclk_bpp; /* * esc clock is byte clock followed by a 4 bit divider,