From patchwork Wed Jul 25 22:29:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 10544887 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D3A66112E for ; Wed, 25 Jul 2018 22:29:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C1E6D2AA28 for ; Wed, 25 Jul 2018 22:29:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B611C2AA2F; Wed, 25 Jul 2018 22:29:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5624C2AA28 for ; Wed, 25 Jul 2018 22:29:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731576AbeGYXmw (ORCPT ); Wed, 25 Jul 2018 19:42:52 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:35503 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731593AbeGYXmv (ORCPT ); Wed, 25 Jul 2018 19:42:51 -0400 Received: by mail-pg1-f195.google.com with SMTP id e6-v6so6202681pgv.2 for ; Wed, 25 Jul 2018 15:29:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GWZK7b9lm024T3/GSjJUtOLt5Sv+N+aSacDYyJvd2YQ=; b=VTr9miTTfbJ4sDN7muGudDUIwoiT5H1w/3UBMvlWD1K1g9tisuV60ZNlkQjOzEz0qa 7ozj5gaxq3dFtZ1560Fg6x3ztcJRYnNzm/374ch27YCAMhGkW4w7/ePpAmB6QhLsa7g3 VRjfZOk9mRcVEt2c5r1PxBP00XXyjcvcXPoLs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GWZK7b9lm024T3/GSjJUtOLt5Sv+N+aSacDYyJvd2YQ=; b=dOJ+WO1GdhLbsvP2z8mOmLxtHIcxUSohl+9A+FiUSka3whhnp4bn8AhkMvwWPPiLsj 23qgxWym5Zw3wf3u4bqdZXtXv5ZfR2QIcDj8B04drVhEWzA+7hJDs+R5nxbD7uC665Z2 CXoapavSdTX8qwl0nazmOzFqErr7YjBtlo6F74SGxYMewDT4D7QsftWqwxho1AY52NPe t7sBPTco8aY5eIVpGU7VqKqQec6AAmL3N6+vn72Jgy/RO3PkwlkacZ0Ols8j2oXSwJ5H avDswTH6NcClReyl1fKAtStFA4TgVY0w2OVcash5+NGL/QsFxW1BYvMWo+NRQZbt8U5b kzlw== X-Gm-Message-State: AOUpUlEDPOPwn9QFMyAJvDPyJQOJcfUy9XjQDYNfqm5c7eCAyHebIkNA cMKK2l+RO8Go1hoGXT+yRkBl7g== X-Google-Smtp-Source: AAOMgpdVI3/vwA1jwld8k23Nkq39S0/+Ft5EaeUHNQKq6G48WIWizq7P/ShbOYvWRgUQHhoLSJkayg== X-Received: by 2002:a62:9cd7:: with SMTP id u84-v6mr24051324pfk.90.1532557745571; Wed, 25 Jul 2018 15:29:05 -0700 (PDT) Received: from swboyd.mtv.corp.google.com ([2620:0:1000:1511:d30e:62c6:f82c:ff40]) by smtp.gmail.com with ESMTPSA id o21-v6sm23839234pfa.54.2018.07.25.15.29.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Jul 2018 15:29:05 -0700 (PDT) From: Stephen Boyd To: Linus Walleij Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, Bjorn Andersson , Doug Anderson Subject: [PATCH v2 3/3] pinctrl: msm: Configure interrupts as input and gpio mode Date: Wed, 25 Jul 2018 15:29:00 -0700 Message-Id: <20180725222900.33231-4-swboyd@chromium.org> X-Mailer: git-send-email 2.18.0.233.g985f88cf7e-goog In-Reply-To: <20180725222900.33231-1-swboyd@chromium.org> References: <20180725222900.33231-1-swboyd@chromium.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When requesting a gpio as an interrupt, we should make sure to mux the pin as the GPIO function and configure it to be an input so that various functions or output signals don't affect the interrupt state of the pin. So far, we've relied on pinmux configurations in DT to handle this, but let's explicitly configure this in the code so that DT implementers don't have to get this part right. Cc: Bjorn Andersson Cc: Doug Anderson Signed-off-by: Stephen Boyd --- Changes from v1: * None drivers/pinctrl/qcom/pinctrl-msm.c | 37 ++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 1d7367149268..f2744092a4bf 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -827,6 +827,41 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) return 0; } +static int msm_gpio_irq_reqres(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + int ret; + + if (!try_module_get(gc->owner)) + return -ENODEV; + + ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); + if (ret) + goto out; + msm_gpio_direction_input(gc, d->hwirq); + + if (gpiochip_lock_as_irq(gc, d->hwirq)) { + dev_err(gc->parent, + "unable to lock HW IRQ %lu for IRQ\n", + d->hwirq); + ret = -EINVAL; + goto out; + } + return 0; +out: + module_put(gc->owner); + return ret; +} + +static void msm_gpio_irq_relres(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + gpiochip_unlock_as_irq(gc, d->hwirq); + module_put(gc->owner); +} + static void msm_gpio_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); @@ -925,6 +960,8 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; + pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; + pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) {