| Message ID | 20180817191026.32245-3-ilina@codeaurora.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Delegated to: | Andy Gross |
| Headers | show |
| Series | Wakeup GPIO support for SDM845 SoC | expand |
Hi Lina, On Fri, 17 Aug 2018 20:10:23 +0100, Lina Iyer <ilina@codeaurora.org> wrote: > > During suspend the system may power down some of the system rails. As a > result, the TLMM hw block may not be operational anymore and wakeup > capable GPIOs will not be detected. The PDC however will be operational > and the GPIOs that are routed to the PDC as IRQs can wake the system up. > > To avoid being interrupted twice (for TLMM and once for PDC IRQ) when a > GPIO trips, use TLMM for active and switch to PDC for suspend. When > entering suspend, disable the TLMM wakeup interrupt and instead enable > the PDC IRQ and revert upon resume. > > Signed-off-by: Lina Iyer <ilina@codeaurora.org> > --- > drivers/pinctrl/qcom/pinctrl-msm.c | 60 +++++++++++++++++++++++++++++- > drivers/pinctrl/qcom/pinctrl-msm.h | 3 ++ > 2 files changed, 62 insertions(+), 1 deletion(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c > index 03ef1d29d078..17e541f8f09d 100644 > --- a/drivers/pinctrl/qcom/pinctrl-msm.c > +++ b/drivers/pinctrl/qcom/pinctrl-msm.c > @@ -37,6 +37,7 @@ > #include "../pinctrl-utils.h" > > #define MAX_NR_GPIO 300 > +#define MAX_PDC_IRQ 1024 Where is this value coming from? Is it guaranteed to be an architectural maximum? Or something that is likely to vary in future implementations? > #define PS_HOLD_OFFSET 0x820 > > /** > @@ -51,6 +52,7 @@ > * @enabled_irqs: Bitmap of currently enabled irqs. > * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge > * detection. > + * @pdc_irqs: Bitmap of wakeup capable irqs. > * @soc; Reference to soc_data of platform specific data. > * @regs: Base address for the TLMM register map. > */ > @@ -68,11 +70,14 @@ struct msm_pinctrl { > > DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); > DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); > + DECLARE_BITMAP(pdc_irqs, MAX_PDC_IRQ); > > const struct msm_pinctrl_soc_data *soc; > void __iomem *regs; > }; > > +static bool in_suspend; > + > static int msm_get_groups_count(struct pinctrl_dev *pctldev) > { > struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); > @@ -787,8 +792,11 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) > > raw_spin_lock_irqsave(&pctrl->lock, flags); > > - if (pdc_irqd) > + if (pdc_irqd && !in_suspend) { > irq_set_irq_wake(pdc_irqd->irq, on); > + on ? set_bit(pdc_irqd->irq, pctrl->pdc_irqs) : > + clear_bit(pdc_irqd->irq, pctrl->pdc_irqs); I think we'll all survive the two extra lines if you write this as an 'if' statement (unless you're competing for the next IOCCC, and then you need to up your game a bit). Also, are you indexing the bitmap using a Linux irq number? If so, that's an absolute NACK. Out of the box, a Linux IRQ can be up to NR_IRQS+8196 on arm64, and there are plans to push that to be a much larger space. > + } > > irq_set_irq_wake(pctrl->irq, on); I'm a bit worried by the way you call into the irq subsystem with this spinlock held. Have you run that code with lockdep enabled? > > @@ -920,6 +928,8 @@ static int msm_gpio_pdc_pin_request(struct irq_data *d) > } > > irq_set_handler_data(d->irq, irq_get_irq_data(irq)); > + irq_set_handler_data(irq, d); > + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); Could you explain what this is trying to do? I'm trying to understand this code, but this function isn't in 4.18... > disable_irq(irq); > > return 0; > @@ -1070,6 +1080,54 @@ static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) > } > } > > +int __maybe_unused msm_pinctrl_suspend_late(struct device *dev) > +{ > + struct msm_pinctrl *pctrl = dev_get_drvdata(dev); > + struct irq_data *irqd; > + int i; > + > + in_suspend = true; > + for_each_set_bit(i, pctrl->pdc_irqs, MAX_PDC_IRQ) { > + irqd = irq_get_handler_data(i); So this is what I though. You're using the Linux IRQ, and not the pin number (or whatever HW-dependent index that would otherwise make sense). Please fix it. > + /* > + * We don't know if the TLMM will be functional > + * or not, during the suspend. If its functional, > + * we do not want duplicate interrupts from PDC. > + * Hence disable the GPIO IRQ and enable PDC IRQ. > + */ > + if (irqd_is_wakeup_set(irqd)) { > + irq_set_irq_wake(irqd->irq, false); > + disable_irq(irqd->irq); > + enable_irq(i); > + } > + } > + > + return 0; > +} > + > +int __maybe_unused msm_pinctrl_resume_late(struct device *dev) > +{ > + struct msm_pinctrl *pctrl = dev_get_drvdata(dev); > + struct irq_data *irqd; > + int i; > + > + for_each_set_bit(i, pctrl->pdc_irqs, MAX_PDC_IRQ) { > + irqd = irq_get_handler_data(i); > + /* > + * The TLMM will be operational now, so disable > + * the PDC IRQ. > + */ > + if (irqd_is_wakeup_set(irq_get_irq_data(i))) { > + disable_irq_nosync(i); > + irq_set_irq_wake(irqd->irq, true); > + enable_irq(irqd->irq); > + } > + } > + in_suspend = false; > + > + return 0; > +} > + > int msm_pinctrl_probe(struct platform_device *pdev, > const struct msm_pinctrl_soc_data *soc_data) > { > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h > index 9b9feea540ff..21b56fb5dae9 100644 > --- a/drivers/pinctrl/qcom/pinctrl-msm.h > +++ b/drivers/pinctrl/qcom/pinctrl-msm.h > @@ -123,4 +123,7 @@ int msm_pinctrl_probe(struct platform_device *pdev, > const struct msm_pinctrl_soc_data *soc_data); > int msm_pinctrl_remove(struct platform_device *pdev); > > +int msm_pinctrl_suspend_late(struct device *dev); > +int msm_pinctrl_resume_late(struct device *dev); > + > #endif I can't really review this code any further, as it seems that I'm missing some crucial dependencies. But there is a number of things that feel quite wrong in this code, and that need to be addressed anyway. Thanks, M.
On Sat, Aug 18 2018 at 07:13 -0600, Marc Zyngier wrote: >Hi Lina, > >On Fri, 17 Aug 2018 20:10:23 +0100, >Lina Iyer <ilina@codeaurora.org> wrote: >> >> During suspend the system may power down some of the system rails. As a >> result, the TLMM hw block may not be operational anymore and wakeup >> capable GPIOs will not be detected. The PDC however will be operational >> and the GPIOs that are routed to the PDC as IRQs can wake the system up. >> >> To avoid being interrupted twice (for TLMM and once for PDC IRQ) when a >> GPIO trips, use TLMM for active and switch to PDC for suspend. When >> entering suspend, disable the TLMM wakeup interrupt and instead enable >> the PDC IRQ and revert upon resume. >> >> Signed-off-by: Lina Iyer <ilina@codeaurora.org> >> --- >> drivers/pinctrl/qcom/pinctrl-msm.c | 60 +++++++++++++++++++++++++++++- >> drivers/pinctrl/qcom/pinctrl-msm.h | 3 ++ >> 2 files changed, 62 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c >> index 03ef1d29d078..17e541f8f09d 100644 >> --- a/drivers/pinctrl/qcom/pinctrl-msm.c >> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c >> @@ -37,6 +37,7 @@ >> #include "../pinctrl-utils.h" >> >> #define MAX_NR_GPIO 300 >> +#define MAX_PDC_IRQ 1024 > >Where is this value coming from? Is it guaranteed to be an >architectural maximum? Or something that is likely to vary in future >implementations? > >> #define PS_HOLD_OFFSET 0x820 >> >> /** >> @@ -51,6 +52,7 @@ >> * @enabled_irqs: Bitmap of currently enabled irqs. >> * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge >> * detection. >> + * @pdc_irqs: Bitmap of wakeup capable irqs. >> * @soc; Reference to soc_data of platform specific data. >> * @regs: Base address for the TLMM register map. >> */ >> @@ -68,11 +70,14 @@ struct msm_pinctrl { >> >> DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); >> DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); >> + DECLARE_BITMAP(pdc_irqs, MAX_PDC_IRQ); >> >> const struct msm_pinctrl_soc_data *soc; >> void __iomem *regs; >> }; >> >> +static bool in_suspend; >> + >> static int msm_get_groups_count(struct pinctrl_dev *pctldev) >> { >> struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); >> @@ -787,8 +792,11 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) >> >> raw_spin_lock_irqsave(&pctrl->lock, flags); >> >> - if (pdc_irqd) >> + if (pdc_irqd && !in_suspend) { >> irq_set_irq_wake(pdc_irqd->irq, on); >> + on ? set_bit(pdc_irqd->irq, pctrl->pdc_irqs) : >> + clear_bit(pdc_irqd->irq, pctrl->pdc_irqs); > >I think we'll all survive the two extra lines if you write this as an >'if' statement (unless you're competing for the next IOCCC, and then >you need to up your game a bit). > >Also, are you indexing the bitmap using a Linux irq number? If so, >that's an absolute NACK. Out of the box, a Linux IRQ can be up to >NR_IRQS+8196 on arm64, and there are plans to push that to be a much >larger space. > I didn't realize this. I have been using linux IRQ number on this bitmask and I will need to fix this. >> + } >> >> irq_set_irq_wake(pctrl->irq, on); > >I'm a bit worried by the way you call into the irq subsystem with this >spinlock held. Have you run that code with lockdep enabled? > I have not tried lockdep. Will try it. This specific line is already part of the driver. I added a similar line irq_set_irq_wake(pdc_irqd->irq) just above following the same pattern. >> >> @@ -920,6 +928,8 @@ static int msm_gpio_pdc_pin_request(struct irq_data *d) >> } >> >> irq_set_handler_data(d->irq, irq_get_irq_data(irq)); >> + irq_set_handler_data(irq, d); >> + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); > >Could you explain what this is trying to do? I'm trying to understand >this code, but this function isn't in 4.18... > Oh, I have been able to test only on 4.14 so far. The flag does seem to exist at least, I didn't get a compiler error. I read this in kernel/irq/chip.c - If the interrupt chip does not implement the irq_disable callback, a driver can disable the lazy approach for a particular irq line by calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can be used for devices which cannot disable the interrupt at the device level under certain circumstances and have to use disable_irq[_nosync] instead. And interpreted this as something that this would prevent 'relaxed' disable. I am enabling and disabling the IRQ in suspend path, that I thought this would help avoid issues caused by late disable. Am I mistaken? >> disable_irq(irq); >> >> return 0; >> @@ -1070,6 +1080,54 @@ static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) >> } >> } >> >> +int __maybe_unused msm_pinctrl_suspend_late(struct device *dev) >> +{ >> + struct msm_pinctrl *pctrl = dev_get_drvdata(dev); >> + struct irq_data *irqd; >> + int i; >> + >> + in_suspend = true; >> + for_each_set_bit(i, pctrl->pdc_irqs, MAX_PDC_IRQ) { >> + irqd = irq_get_handler_data(i); > >So this is what I though. You're using the Linux IRQ, and not the pin >number (or whatever HW-dependent index that would otherwise make >sense). Please fix it. > Noted. >> + /* >> + * We don't know if the TLMM will be functional >> + * or not, during the suspend. If its functional, >> + * we do not want duplicate interrupts from PDC. >> + * Hence disable the GPIO IRQ and enable PDC IRQ. >> + */ >> + if (irqd_is_wakeup_set(irqd)) { >> + irq_set_irq_wake(irqd->irq, false); >> + disable_irq(irqd->irq); >> + enable_irq(i); >> + } >> + } >> + >> + return 0; >> +} >> + >> +int __maybe_unused msm_pinctrl_resume_late(struct device *dev) >> +{ >> + struct msm_pinctrl *pctrl = dev_get_drvdata(dev); >> + struct irq_data *irqd; >> + int i; >> + >> + for_each_set_bit(i, pctrl->pdc_irqs, MAX_PDC_IRQ) { >> + irqd = irq_get_handler_data(i); >> + /* >> + * The TLMM will be operational now, so disable >> + * the PDC IRQ. >> + */ >> + if (irqd_is_wakeup_set(irq_get_irq_data(i))) { >> + disable_irq_nosync(i); >> + irq_set_irq_wake(irqd->irq, true); >> + enable_irq(irqd->irq); >> + } >> + } >> + in_suspend = false; >> + >> + return 0; >> +} >> + >> int msm_pinctrl_probe(struct platform_device *pdev, >> const struct msm_pinctrl_soc_data *soc_data) >> { >> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h >> index 9b9feea540ff..21b56fb5dae9 100644 >> --- a/drivers/pinctrl/qcom/pinctrl-msm.h >> +++ b/drivers/pinctrl/qcom/pinctrl-msm.h >> @@ -123,4 +123,7 @@ int msm_pinctrl_probe(struct platform_device *pdev, >> const struct msm_pinctrl_soc_data *soc_data); >> int msm_pinctrl_remove(struct platform_device *pdev); >> >> +int msm_pinctrl_suspend_late(struct device *dev); >> +int msm_pinctrl_resume_late(struct device *dev); >> + >> #endif > >I can't really review this code any further, as it seems that I'm >missing some crucial dependencies. But there is a number of things >that feel quite wrong in this code, and that need to be addressed >anyway. > Thanks for reviewing Marc. -- Lina
On 20/08/18 16:26, Lina Iyer wrote: > On Sat, Aug 18 2018 at 07:13 -0600, Marc Zyngier wrote: >> Hi Lina, >> >> On Fri, 17 Aug 2018 20:10:23 +0100, >> Lina Iyer <ilina@codeaurora.org> wrote: [...] >>> @@ -920,6 +928,8 @@ static int msm_gpio_pdc_pin_request(struct irq_data *d) >>> } >>> >>> irq_set_handler_data(d->irq, irq_get_irq_data(irq)); >>> + irq_set_handler_data(irq, d); >>> + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); >> >> Could you explain what this is trying to do? I'm trying to understand >> this code, but this function isn't in 4.18... >> > Oh, I have been able to test only on 4.14 so far. The flag does seem to > exist at least, I didn't get a compiler error. > > I read this in kernel/irq/chip.c - > > If the interrupt chip does not implement the irq_disable callback, > a driver can disable the lazy approach for a particular irq line by > calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can > be used for devices which cannot disable the interrupt at the > device level under certain circumstances and have to use > disable_irq[_nosync] instead. > > And interpreted this as something that this would prevent 'relaxed' > disable. I am enabling and disabling the IRQ in suspend path, that I > thought this would help avoid issues caused by late disable. Am I > mistaken? Sorry, I wasn't clear enough. I'm talking about what you're trying to do in this particular function (msm_gpio_pdc_pin_request), which doesn't exist in 4.18. Short of having a bit of context, I can hardly review this. Thanks, M.
On Mon, Aug 20 2018 at 09:34 -0600, Marc Zyngier wrote: >On 20/08/18 16:26, Lina Iyer wrote: >> On Sat, Aug 18 2018 at 07:13 -0600, Marc Zyngier wrote: >>> Hi Lina, >>> >>> On Fri, 17 Aug 2018 20:10:23 +0100, >>> Lina Iyer <ilina@codeaurora.org> wrote: > >[...] > >>>> @@ -920,6 +928,8 @@ static int msm_gpio_pdc_pin_request(struct irq_data *d) >>>> } >>>> >>>> irq_set_handler_data(d->irq, irq_get_irq_data(irq)); >>>> + irq_set_handler_data(irq, d); >>>> + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); >>> >>> Could you explain what this is trying to do? I'm trying to understand >>> this code, but this function isn't in 4.18... >>> >> Oh, I have been able to test only on 4.14 so far. The flag does seem to >> exist at least, I didn't get a compiler error. >> >> I read this in kernel/irq/chip.c - >> >> If the interrupt chip does not implement the irq_disable callback, >> a driver can disable the lazy approach for a particular irq line by >> calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can >> be used for devices which cannot disable the interrupt at the >> device level under certain circumstances and have to use >> disable_irq[_nosync] instead. >> >> And interpreted this as something that this would prevent 'relaxed' >> disable. I am enabling and disabling the IRQ in suspend path, that I >> thought this would help avoid issues caused by late disable. Am I >> mistaken? > >Sorry, I wasn't clear enough. I'm talking about what you're trying to do >in this particular function (msm_gpio_pdc_pin_request), which doesn't >exist in 4.18. Short of having a bit of context, I can hardly review this. > Sorry, my patch generation during the resend is messed up. Seems like I didn't send that patch out during the resend. -- Lina
On Mon, 20 Aug 2018 09:49:59 -0600 Lina Iyer <ilina@codeaurora.org> wrote: > On Mon, Aug 20 2018 at 09:34 -0600, Marc Zyngier wrote: > >On 20/08/18 16:26, Lina Iyer wrote: > >> On Sat, Aug 18 2018 at 07:13 -0600, Marc Zyngier wrote: > >>> Hi Lina, > >>> > >>> On Fri, 17 Aug 2018 20:10:23 +0100, > >>> Lina Iyer <ilina@codeaurora.org> wrote: > > > >[...] > > > >>>> @@ -920,6 +928,8 @@ static int msm_gpio_pdc_pin_request(struct irq_data *d) > >>>> } > >>>> > >>>> irq_set_handler_data(d->irq, irq_get_irq_data(irq)); > >>>> + irq_set_handler_data(irq, d); > >>>> + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); > >>> > >>> Could you explain what this is trying to do? I'm trying to understand > >>> this code, but this function isn't in 4.18... > >>> > >> Oh, I have been able to test only on 4.14 so far. The flag does seem to > >> exist at least, I didn't get a compiler error. > >> > >> I read this in kernel/irq/chip.c - > >> > >> If the interrupt chip does not implement the irq_disable callback, > >> a driver can disable the lazy approach for a particular irq line by > >> calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can > >> be used for devices which cannot disable the interrupt at the > >> device level under certain circumstances and have to use > >> disable_irq[_nosync] instead. > >> > >> And interpreted this as something that this would prevent 'relaxed' > >> disable. I am enabling and disabling the IRQ in suspend path, that I > >> thought this would help avoid issues caused by late disable. Am I > >> mistaken? > > > >Sorry, I wasn't clear enough. I'm talking about what you're trying to do > >in this particular function (msm_gpio_pdc_pin_request), which doesn't > >exist in 4.18. Short of having a bit of context, I can hardly review this. > > > Sorry, my patch generation during the resend is messed up. Seems like I > didn't send that patch out during the resend. Please make sure you test with mainline. Basing your developments on something as old as 4.14 makes no sense for something that targets mainline. You should write your code on mainline, test it there, and eventually backport it to whatever version you want to use. Otherwise, we are guaranteed to merge something that will not work. Thanks, M.
Quoting Lina Iyer (2018-08-17 12:10:23) > During suspend the system may power down some of the system rails. As a > result, the TLMM hw block may not be operational anymore and wakeup > capable GPIOs will not be detected. The PDC however will be operational > and the GPIOs that are routed to the PDC as IRQs can wake the system up. > > To avoid being interrupted twice (for TLMM and once for PDC IRQ) when a > GPIO trips, use TLMM for active and switch to PDC for suspend. When > entering suspend, disable the TLMM wakeup interrupt and instead enable > the PDC IRQ and revert upon resume. What about idle paths? Don't we want to disable the TLMM interrupt and enable the PDC interrupt when the whole cluster goes idle so we get wakeup interrupts? It's really unfortunate that the hardware can't replay the interrupt from PDC to TLMM when it knows TLMM didn't get the interrupt (because the whole chip was off) or the GIC didn't get the summary irq (because the GIC was powered off). A little more hardware effort would make this completely transparent to software and make TLMM work across all low power modes. Because of this complicated dance, it may make sense to always get the interrupt at the PDC and then replay it into the TLMM chip "manually" with the irq_set_irqchip_state() APIs. This way the duplicate interrupt can't happen. The only way for the interrupt handler to run would be by PDC poking the TLMM hardware to inject the irq into the status register. I think with the TLMM that's possible if we configure the pin to have the raw status bit disabled (so that edges on the physical line don't latch into the GPIO interrupt status register) and the normal status bit enabled (so that if the status register changes we'll interrupt the CPU). It needs some testing to make sure that actually works though. If it does work, then we have a way to inject interrupts on TLMM without worry that the TLMM hardware will also see the interrupt. Is there a good way to test an interrupt to see if it's edge or level type configured? And is it really a problem to make PDC the hierarchical parent of TLMM here so that PDC can intercept the type and wake state of the GPIO irq? Plus there's the part where a GIC SPI interrupt runs for some GPIO irq, and that needs to be decoded to figure out which GPIO it is for and if it should be replayed or not. Maybe all types of GPIO irqs can be replayed and if it's a level type interrupt we waste some time handling the PDC interrupt just to do nothing besides forward what would presumably already work without PDC intervention.
On Fri, Aug 24 2018 at 02:22 -0600, Stephen Boyd wrote: >Quoting Lina Iyer (2018-08-17 12:10:23) >> During suspend the system may power down some of the system rails. As a >> result, the TLMM hw block may not be operational anymore and wakeup >> capable GPIOs will not be detected. The PDC however will be operational >> and the GPIOs that are routed to the PDC as IRQs can wake the system up. >> >> To avoid being interrupted twice (for TLMM and once for PDC IRQ) when a >> GPIO trips, use TLMM for active and switch to PDC for suspend. When >> entering suspend, disable the TLMM wakeup interrupt and instead enable >> the PDC IRQ and revert upon resume. > >What about idle paths? Don't we want to disable the TLMM interrupt and >enable the PDC interrupt when the whole cluster goes idle so we get >wakeup interrupts? We would need to do this from the idle paths. When we have that support (a patch for cluster power down is in the works), we would need to hook up to TLMM and do the same. >It's really unfortunate that the hardware can't >replay the interrupt from PDC to TLMM when it knows TLMM didn't get the >interrupt (because the whole chip was off) or the GIC didn't get the >summary irq (because the GIC was powered off). A little more hardware >effort would make this completely transparent to software and make TLMM >work across all low power modes. > I wouln't pretend to understand what it entails in the hardware. But, I believe the complication stems from the fact that PDC is sensing the raw GPIO just as TLMM when active and sensing itself. To know when to replay only the interrupt lines for the TLMM (knowing the TLMM was powered off) might be a lot of hardware. >Because of this complicated dance, it may make sense to always get the >interrupt at the PDC and then replay it into the TLMM chip "manually" >with the irq_set_irqchip_state() APIs. This way the duplicate interrupt >can't happen. The only way for the interrupt handler to run would be by >PDC poking the TLMM hardware to inject the irq into the status register. If the PDC interrupt was always enabled and the interrupt at TLMM was always disabled, all we would need to set the action handler of the PDC interrupt to that of the TLMM. I couldn't find a way to retrieve that nicely. >I think with the TLMM that's possible if we configure the pin to have >the raw status bit disabled (so that edges on the physical line don't >latch into the GPIO interrupt status register) and the normal status bit >enabled (so that if the status register changes we'll interrupt the >CPU). It needs some testing to make sure that actually works though. If >it does work, then we have a way to inject interrupts on TLMM without >worry that the TLMM hardware will also see the interrupt. > >Is there a good way to test an interrupt to see if it's edge or level >type configured? And is it really a problem to make PDC the hierarchical >parent of TLMM here so that PDC can intercept the type and wake state of >the GPIO irq? Alternately, could we just return the PDC interrupt in gpio_to_irq() and let the driver manipulate only the PDC interrupt ? Ofcourse, drivers that request the GPIO as interrupt in DT, would now have to request the PDC interrupt directly. That could avoid the dance during every idle/suspend. I am not sure how nice it is do this, would like to know your thoughts. >Plus there's the part where a GIC SPI interrupt runs for >some GPIO irq, and that needs to be decoded to figure out which GPIO it >is for and if it should be replayed or not. Maybe all types of GPIO irqs >can be replayed and if it's a level type interrupt we waste some time >handling the PDC interrupt just to do nothing besides forward what would >presumably already work without PDC intervention. >
Quoting Lina Iyer (2018-08-24 10:14:32) > On Fri, Aug 24 2018 at 02:22 -0600, Stephen Boyd wrote: > >Quoting Lina Iyer (2018-08-17 12:10:23) > >> During suspend the system may power down some of the system rails. As a > >> result, the TLMM hw block may not be operational anymore and wakeup > >> capable GPIOs will not be detected. The PDC however will be operational > >> and the GPIOs that are routed to the PDC as IRQs can wake the system up. > >> > >> To avoid being interrupted twice (for TLMM and once for PDC IRQ) when a > >> GPIO trips, use TLMM for active and switch to PDC for suspend. When > >> entering suspend, disable the TLMM wakeup interrupt and instead enable > >> the PDC IRQ and revert upon resume. > > > >What about idle paths? Don't we want to disable the TLMM interrupt and > >enable the PDC interrupt when the whole cluster goes idle so we get > >wakeup interrupts? > We would need to do this from the idle paths. When we have that support > (a patch for cluster power down is in the works), we would need to hook > up to TLMM and do the same. Ok so then this approach doesn't really seem to work for the CPU idle paths. > >Because of this complicated dance, it may make sense to always get the > >interrupt at the PDC and then replay it into the TLMM chip "manually" > >with the irq_set_irqchip_state() APIs. This way the duplicate interrupt > >can't happen. The only way for the interrupt handler to run would be by > >PDC poking the TLMM hardware to inject the irq into the status register. > If the PDC interrupt was always enabled and the interrupt at TLMM was > always disabled, all we would need to set the action handler of the PDC > interrupt to that of the TLMM. I couldn't find a way to retrieve that > nicely. Can't we just configure a different chained IRQ handler with irq_set_chained_handler_and_data() for each of the GPIO IRQs that are handled by PDC to be the interrupts provide by the PDC irq controller that match the GPIOs? And then set their parent irq with irq_set_parent() for completeness? And also move those GPIOs from the existing msm_gpio irqchip to a different PDC gpio irqchip that does nothing besides push irqchip calls up to the PDC irqchip? Then we don't even have to think about resending anything and we can rely on PDC to do all the interrupt sensing all the time but still provide the irqs from the GPIO controller. > > >I think with the TLMM that's possible if we configure the pin to have > >the raw status bit disabled (so that edges on the physical line don't > >latch into the GPIO interrupt status register) and the normal status bit > >enabled (so that if the status register changes we'll interrupt the > >CPU). It needs some testing to make sure that actually works though. If > >it does work, then we have a way to inject interrupts on TLMM without > >worry that the TLMM hardware will also see the interrupt. > > > > >Is there a good way to test an interrupt to see if it's edge or level > >type configured? And is it really a problem to make PDC the hierarchical > >parent of TLMM here so that PDC can intercept the type and wake state of > >the GPIO irq? > Alternately, could we just return the PDC interrupt in gpio_to_irq() and > let the driver manipulate only the PDC interrupt ? Ofcourse, drivers > that request the GPIO as interrupt in DT, would now have to request the > PDC interrupt directly. That could avoid the dance during every > idle/suspend. I am not sure how nice it is do this, would like to know > your thoughts. > I hope it doesn't come to that.
On Mon, Aug 27 2018 at 14:01 -0600, Stephen Boyd wrote: >Quoting Lina Iyer (2018-08-24 10:14:32) >> On Fri, Aug 24 2018 at 02:22 -0600, Stephen Boyd wrote: >> >Quoting Lina Iyer (2018-08-17 12:10:23) >> >> During suspend the system may power down some of the system rails. As a >> >> result, the TLMM hw block may not be operational anymore and wakeup >> >> capable GPIOs will not be detected. The PDC however will be operational >> >> and the GPIOs that are routed to the PDC as IRQs can wake the system up. >> >> >> >> To avoid being interrupted twice (for TLMM and once for PDC IRQ) when a >> >> GPIO trips, use TLMM for active and switch to PDC for suspend. When >> >> entering suspend, disable the TLMM wakeup interrupt and instead enable >> >> the PDC IRQ and revert upon resume. >> > >> >What about idle paths? Don't we want to disable the TLMM interrupt and >> >enable the PDC interrupt when the whole cluster goes idle so we get >> >wakeup interrupts? >> We would need to do this from the idle paths. When we have that support >> (a patch for cluster power down is in the works), we would need to hook >> up to TLMM and do the same. > >Ok so then this approach doesn't really seem to work for the CPU idle >paths. > >> >Because of this complicated dance, it may make sense to always get the >> >interrupt at the PDC and then replay it into the TLMM chip "manually" >> >with the irq_set_irqchip_state() APIs. This way the duplicate interrupt >> >can't happen. The only way for the interrupt handler to run would be by >> >PDC poking the TLMM hardware to inject the irq into the status register. >> If the PDC interrupt was always enabled and the interrupt at TLMM was >> always disabled, all we would need to set the action handler of the PDC >> interrupt to that of the TLMM. I couldn't find a way to retrieve that >> nicely. > >Can't we just configure a different chained IRQ handler with >irq_set_chained_handler_and_data() for each of the GPIO IRQs that are >handled by PDC to be the interrupts provide by the PDC irq controller >that match the GPIOs? And then set their parent irq with >irq_set_parent() for completeness? And also move those GPIOs from the >existing msm_gpio irqchip to a different PDC gpio irqchip that does >nothing besides push irqchip calls up to the PDC irqchip? Then we don't >even have to think about resending anything and we can rely on PDC to do >all the interrupt sensing all the time but still provide the irqs from >the GPIO controller. > Seems like the irqchips need to be in hierarchy for this to work, which is not the case with TLMM and the PDC, currently. -- Lina
Quoting Lina Iyer (2018-09-04 14:09:34) > On Mon, Aug 27 2018 at 14:01 -0600, Stephen Boyd wrote: > > > >Can't we just configure a different chained IRQ handler with > >irq_set_chained_handler_and_data() for each of the GPIO IRQs that are > >handled by PDC to be the interrupts provide by the PDC irq controller > >that match the GPIOs? And then set their parent irq with > >irq_set_parent() for completeness? And also move those GPIOs from the > >existing msm_gpio irqchip to a different PDC gpio irqchip that does > >nothing besides push irqchip calls up to the PDC irqchip? Then we don't > >even have to think about resending anything and we can rely on PDC to do > >all the interrupt sensing all the time but still provide the irqs from > >the GPIO controller. > > > Seems like the irqchips need to be in hierarchy for this to work, which > is not the case with TLMM and the PDC, currently. > Why? Does something mandate that the chained irq is also the hierarchical parent irqchip?
On Tue, Sep 04 2018 at 16:00 -0600, Stephen Boyd wrote: >Quoting Lina Iyer (2018-09-04 14:09:34) >> On Mon, Aug 27 2018 at 14:01 -0600, Stephen Boyd wrote: >> > >> >Can't we just configure a different chained IRQ handler with >> >irq_set_chained_handler_and_data() for each of the GPIO IRQs that are >> >handled by PDC to be the interrupts provide by the PDC irq controller >> >that match the GPIOs? And then set their parent irq with >> >irq_set_parent() for completeness? And also move those GPIOs from the >> >existing msm_gpio irqchip to a different PDC gpio irqchip that does >> >nothing besides push irqchip calls up to the PDC irqchip? Then we don't >> >even have to think about resending anything and we can rely on PDC to do >> >all the interrupt sensing all the time but still provide the irqs from >> >the GPIO controller. >> > >> Seems like the irqchips need to be in hierarchy for this to work, which >> is not the case with TLMM and the PDC, currently. >> > >Why? Does something mandate that the chained irq is also the >hierarchical parent irqchip? > All the _parent() functions like irq_set_wake_parent() etc need parent_data to be set, which is only set during hierarchy. -- Lina
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 03ef1d29d078..17e541f8f09d 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -37,6 +37,7 @@ #include "../pinctrl-utils.h" #define MAX_NR_GPIO 300 +#define MAX_PDC_IRQ 1024 #define PS_HOLD_OFFSET 0x820 /** @@ -51,6 +52,7 @@ * @enabled_irqs: Bitmap of currently enabled irqs. * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge * detection. + * @pdc_irqs: Bitmap of wakeup capable irqs. * @soc; Reference to soc_data of platform specific data. * @regs: Base address for the TLMM register map. */ @@ -68,11 +70,14 @@ struct msm_pinctrl { DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); + DECLARE_BITMAP(pdc_irqs, MAX_PDC_IRQ); const struct msm_pinctrl_soc_data *soc; void __iomem *regs; }; +static bool in_suspend; + static int msm_get_groups_count(struct pinctrl_dev *pctldev) { struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -787,8 +792,11 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) raw_spin_lock_irqsave(&pctrl->lock, flags); - if (pdc_irqd) + if (pdc_irqd && !in_suspend) { irq_set_irq_wake(pdc_irqd->irq, on); + on ? set_bit(pdc_irqd->irq, pctrl->pdc_irqs) : + clear_bit(pdc_irqd->irq, pctrl->pdc_irqs); + } irq_set_irq_wake(pctrl->irq, on); @@ -920,6 +928,8 @@ static int msm_gpio_pdc_pin_request(struct irq_data *d) } irq_set_handler_data(d->irq, irq_get_irq_data(irq)); + irq_set_handler_data(irq, d); + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); disable_irq(irq); return 0; @@ -1070,6 +1080,54 @@ static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) } } +int __maybe_unused msm_pinctrl_suspend_late(struct device *dev) +{ + struct msm_pinctrl *pctrl = dev_get_drvdata(dev); + struct irq_data *irqd; + int i; + + in_suspend = true; + for_each_set_bit(i, pctrl->pdc_irqs, MAX_PDC_IRQ) { + irqd = irq_get_handler_data(i); + /* + * We don't know if the TLMM will be functional + * or not, during the suspend. If its functional, + * we do not want duplicate interrupts from PDC. + * Hence disable the GPIO IRQ and enable PDC IRQ. + */ + if (irqd_is_wakeup_set(irqd)) { + irq_set_irq_wake(irqd->irq, false); + disable_irq(irqd->irq); + enable_irq(i); + } + } + + return 0; +} + +int __maybe_unused msm_pinctrl_resume_late(struct device *dev) +{ + struct msm_pinctrl *pctrl = dev_get_drvdata(dev); + struct irq_data *irqd; + int i; + + for_each_set_bit(i, pctrl->pdc_irqs, MAX_PDC_IRQ) { + irqd = irq_get_handler_data(i); + /* + * The TLMM will be operational now, so disable + * the PDC IRQ. + */ + if (irqd_is_wakeup_set(irq_get_irq_data(i))) { + disable_irq_nosync(i); + irq_set_irq_wake(irqd->irq, true); + enable_irq(irqd->irq); + } + } + in_suspend = false; + + return 0; +} + int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data) { diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 9b9feea540ff..21b56fb5dae9 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -123,4 +123,7 @@ int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data); int msm_pinctrl_remove(struct platform_device *pdev); +int msm_pinctrl_suspend_late(struct device *dev); +int msm_pinctrl_resume_late(struct device *dev); + #endif
During suspend the system may power down some of the system rails. As a result, the TLMM hw block may not be operational anymore and wakeup capable GPIOs will not be detected. The PDC however will be operational and the GPIOs that are routed to the PDC as IRQs can wake the system up. To avoid being interrupted twice (for TLMM and once for PDC IRQ) when a GPIO trips, use TLMM for active and switch to PDC for suspend. When entering suspend, disable the TLMM wakeup interrupt and instead enable the PDC IRQ and revert upon resume. Signed-off-by: Lina Iyer <ilina@codeaurora.org> --- drivers/pinctrl/qcom/pinctrl-msm.c | 60 +++++++++++++++++++++++++++++- drivers/pinctrl/qcom/pinctrl-msm.h | 3 ++ 2 files changed, 62 insertions(+), 1 deletion(-)