From patchwork Fri Oct 5 20:06:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10628703 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D0AB9933 for ; Fri, 5 Oct 2018 20:06:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C191C29BC4 for ; Fri, 5 Oct 2018 20:06:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B5D5929C2E; Fri, 5 Oct 2018 20:06:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5BA5629BC4 for ; Fri, 5 Oct 2018 20:06:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728314AbeJFDG0 (ORCPT ); Fri, 5 Oct 2018 23:06:26 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:46474 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728160AbeJFDG0 (ORCPT ); Fri, 5 Oct 2018 23:06:26 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id B619960265; Fri, 5 Oct 2018 20:06:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1538769969; bh=V8g4B7eDiKx0x/xUKNvvIr38F1GsSS2hBpNbVZfywy8=; h=From:To:Cc:Subject:Date:From; b=ODY6pYVKEcRIjCJJxe/Mz4VxU1H37XQHCTdJiw6f1RAkpPrDnR0gChYm9+jdWyPob zS4Kyxh2aCc6ISUOlubJjri6DIY2hqG/G1DBZg5qilPFMvcY2TyIp+ZdWqMr1uDh0U aus0ZooP3g9MITkoHrzNjJuIV8yZprn2tnNWF3e8= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id F1C46605FF; Fri, 5 Oct 2018 20:06:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1538769969; bh=V8g4B7eDiKx0x/xUKNvvIr38F1GsSS2hBpNbVZfywy8=; h=From:To:Cc:Subject:Date:From; b=ODY6pYVKEcRIjCJJxe/Mz4VxU1H37XQHCTdJiw6f1RAkpPrDnR0gChYm9+jdWyPob zS4Kyxh2aCc6ISUOlubJjri6DIY2hqG/G1DBZg5qilPFMvcY2TyIp+ZdWqMr1uDh0U aus0ZooP3g9MITkoHrzNjJuIV8yZprn2tnNWF3e8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org F1C46605FF Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH] drm/msm/a6xx: Remove CP perfcounter selects from the protected list Date: Fri, 5 Oct 2018 14:06:05 -0600 Message-Id: <20181005200605.30175-1-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The CP performance counter selects were accidentally marked as protected so they couldn't be written from PM4 streams. Remove the protection because user space does have an interest in setting up their own counters. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index de01e6553999..cd67f45dee6e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -440,10 +440,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d)); gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76)); gpu_write(gpu, REG_A6XX_CP_PROTECT(24), - A6XX_PROTECT_RDONLY(0x8d0, 0x23)); - gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RDONLY(0x980, 0x4)); - gpu_write(gpu, REG_A6XX_CP_PROTECT(26), A6XX_PROTECT_RW(0xa630, 0x0)); + gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0)); /* Enable interrupts */ gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK);