| Message ID | 20181105154529.7614-12-vkoul@kernel.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Delegated to: | Andy Gross |
| Headers | show |
| Series | arm64: dts: qcom: qcs404: Add Device tree nodes | expand |
On Mon 05 Nov 07:45 PST 2018, Vinod Koul wrote: > Add the GPIOs present on PMS405 chip. > > Signed-off-by: Vinod Koul <vkoul@kernel.org> > --- > arch/arm64/boot/dts/qcom/pms405.dtsi | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi > index cdb4547c998b..18410d9f0f8f 100644 > --- a/arch/arm64/boot/dts/qcom/pms405.dtsi > +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi > @@ -17,5 +17,21 @@ > reg-names = "rtc", "alarm"; > interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; > }; > + > + pms405_gpios: gpios@c000 { > + compatible = "qcom,pms405-gpio"; > + reg = <0xc000>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupts = <0 0xc1 0 IRQ_TYPE_NONE>, > + <0 0xc2 0 IRQ_TYPE_NONE>, > + <0 0xc3 0 IRQ_TYPE_NONE>, > + <0 0xc4 0 IRQ_TYPE_NONE>, > + <0 0xc5 0 IRQ_TYPE_NONE>, > + <0 0xc6 0 IRQ_TYPE_NONE>, > + <0 0xc7 0 IRQ_TYPE_NONE>, > + <0 0xca 0 IRQ_TYPE_NONE>, > + <0 0xcb 0 IRQ_TYPE_NONE>; Is there a reason why gpio 1, 8 and 9 are omitted from this list? Regards, Bjorn > + }; > }; > }; > -- > 2.14.4 >
On 05-11-18, 11:08, Bjorn Andersson wrote: > On Mon 05 Nov 07:45 PST 2018, Vinod Koul wrote: > > > Add the GPIOs present on PMS405 chip. > > > > Signed-off-by: Vinod Koul <vkoul@kernel.org> > > --- > > arch/arm64/boot/dts/qcom/pms405.dtsi | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi > > index cdb4547c998b..18410d9f0f8f 100644 > > --- a/arch/arm64/boot/dts/qcom/pms405.dtsi > > +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi > > @@ -17,5 +17,21 @@ > > reg-names = "rtc", "alarm"; > > interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; > > }; > > + > > + pms405_gpios: gpios@c000 { > > + compatible = "qcom,pms405-gpio"; > > + reg = <0xc000>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupts = <0 0xc1 0 IRQ_TYPE_NONE>, > > + <0 0xc2 0 IRQ_TYPE_NONE>, > > + <0 0xc3 0 IRQ_TYPE_NONE>, > > + <0 0xc4 0 IRQ_TYPE_NONE>, > > + <0 0xc5 0 IRQ_TYPE_NONE>, > > + <0 0xc6 0 IRQ_TYPE_NONE>, > > + <0 0xc7 0 IRQ_TYPE_NONE>, > > + <0 0xca 0 IRQ_TYPE_NONE>, > > + <0 0xcb 0 IRQ_TYPE_NONE>; > > Is there a reason why gpio 1, 8 and 9 are omitted from this list? I think I saw something in downstream code / documentation for this, I will check again to be sure
diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index cdb4547c998b..18410d9f0f8f 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -17,5 +17,21 @@ reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; }; + + pms405_gpios: gpios@c000 { + compatible = "qcom,pms405-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xc1 0 IRQ_TYPE_NONE>, + <0 0xc2 0 IRQ_TYPE_NONE>, + <0 0xc3 0 IRQ_TYPE_NONE>, + <0 0xc4 0 IRQ_TYPE_NONE>, + <0 0xc5 0 IRQ_TYPE_NONE>, + <0 0xc6 0 IRQ_TYPE_NONE>, + <0 0xc7 0 IRQ_TYPE_NONE>, + <0 0xca 0 IRQ_TYPE_NONE>, + <0 0xcb 0 IRQ_TYPE_NONE>; + }; }; };
Add the GPIOs present on PMS405 chip. Signed-off-by: Vinod Koul <vkoul@kernel.org> --- arch/arm64/boot/dts/qcom/pms405.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)