diff mbox series

[v1,2/3] arm64: dts: qcom: sdm845: Add SD nodes

Message ID 20181128223428.177313-3-evgreen@chromium.org (mailing list archive)
State Not Applicable, archived
Headers show
Series arm64: dts: qcom: sdm845: Add SD nodes | expand

Commit Message

Evan Green Nov. 28, 2018, 10:34 p.m. UTC
Add the SD controller to SDM845.

Signed-off-by: Evan Green <evgreen@chromium.org>
---

 arch/arm64/boot/dts/qcom/sdm845.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Comments

Doug Anderson Dec. 5, 2018, 9:07 p.m. UTC | #1
Hi,

On Wed, Nov 28, 2018 at 2:34 PM Evan Green <evgreen@chromium.org> wrote:
>
> Add the SD controller to SDM845.
>
> Signed-off-by: Evan Green <evgreen@chromium.org>
> ---
>
>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)

Looks right to me.  Possibly you might want to make it known in the
subject and description that this is only sdhc_2 since there are two
SD controllers in SDM845 (oddly numbered sdc2 and sdc4 in the
documentation).  sdc2 (the one you're supporting here) is the
dual-voltage one (supports higher speeds) and also the only one hooked
up on MTP I think.  ...so maybe nobody will ever use sdhc_4, but it
might be worth mentioning anyway.  ;-)

Other than that suggestion this looks good to me.

[note to Andy: please double-check that this ends up in the right sort
order when applying.  If you happen to apply the Quad SPI patch first
then "git am" might end up putting the SDHC_2 node _after_ the Quad
SPI but it should sort numerically before it]

Reviewed-by: Douglas Anderson <dianders@chromium.org>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 1419b0098cb38..bb8eacdf40910 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1078,6 +1078,21 @@ 
 			};
 		};
 
+		sdhc_2: sdhci@8804000 {
+			compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0x8804000 0x1000>;
+
+			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC2_APPS_CLK>;
+			clock-names = "iface", "core";
+
+			status = "disabled";
+		};
+
 		usb_1_hsphy: phy@88e2000 {
 			compatible = "qcom,sdm845-qusb2-phy";
 			reg = <0x88e2000 0x400>;