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[158.174.22.210]) by smtp.gmail.com with ESMTPSA id j76-v6sm393983ljb.12.2018.11.29.09.47.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Nov 2018 09:47:54 -0800 (PST) From: Ulf Hansson To: "Rafael J . Wysocki" , Sudeep Holla , Lorenzo Pieralisi , Mark Rutland , Daniel Lezcano , linux-pm@vger.kernel.org Cc: "Raju P . L . S . S . S . N" , Stephen Boyd , Tony Lindgren , Kevin Hilman , Lina Iyer , Ulf Hansson , Viresh Kumar , Vincent Guittot , Geert Uytterhoeven , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Lina Iyer , Andy Gross , David Brown Subject: [PATCH v10 26/27] arm64: dts: Convert to the hierarchical CPU topology layout for MSM8916 Date: Thu, 29 Nov 2018 18:46:59 +0100 Message-Id: <20181129174700.16585-27-ulf.hansson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181129174700.16585-1-ulf.hansson@linaro.org> References: <20181129174700.16585-1-ulf.hansson@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Lina Iyer In the hierarchical layout, we are creating power domains around each CPU and describes the idle states for them inside the power domain provider node. Note that, the CPU's idle states still needs to be compatible with "arm,idle-state". Furthermore, represent the CPU cluster as a separate master power domain, powering the CPU's power domains. The cluster node, contains the idle states for the cluster and each idle state needs to be compatible with the "domain-idle-state". If the running platform is using a PSCI FW that supports the OS initiated CPU suspend mode, which likely should be the case unless the PSCI FW is very old, this change triggers the PSCI driver to enable it. Cc: Andy Gross Cc: David Brown Cc: Lina Iyer Signed-off-by: Lina Iyer Co-developed-by: Ulf Hansson Signed-off-by: Ulf Hansson --- Changes in v10: - Added power-domain-names property to the CPU nodes, as to avoid possible future churns, if ever multiple power-domains specifiers. --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 57 +++++++++++++++++++++++++-- 1 file changed, 53 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d302d8d639a1..cfafce4bfdf0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -110,10 +110,11 @@ reg = <0x0>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SPC>; clocks = <&apcs 0>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; }; CPU1: cpu@1 { @@ -122,10 +123,11 @@ reg = <0x1>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SPC>; clocks = <&apcs 0>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; }; CPU2: cpu@2 { @@ -134,10 +136,11 @@ reg = <0x2>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SPC>; clocks = <&apcs 0>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; }; CPU3: cpu@3 { @@ -146,10 +149,11 @@ reg = <0x3>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SPC>; clocks = <&apcs 0>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; }; L2_0: l2-cache { @@ -166,12 +170,57 @@ min-residency-us = <2000>; local-timer-stop; }; + + CLUSTER_RET: cluster-retention { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000010>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWRDN: cluster-gdhs { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000030>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SPC>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SPC>; + }; + + CPU_PD2: cpu-pd2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SPC>; + }; + + CPU_PD3: cpu-pd3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SPC>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; + }; }; pmu {