From patchwork Wed Dec 12 09:21:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 10725803 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E8B9D1869 for ; Wed, 12 Dec 2018 09:26:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D9BA9283C7 for ; Wed, 12 Dec 2018 09:26:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CDF5429F10; Wed, 12 Dec 2018 09:26:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B390283C7 for ; Wed, 12 Dec 2018 09:26:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726912AbeLLJZh (ORCPT ); Wed, 12 Dec 2018 04:25:37 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:55452 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726903AbeLLJZh (ORCPT ); Wed, 12 Dec 2018 04:25:37 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 631E26014B; Wed, 12 Dec 2018 09:25:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1544606736; bh=M/OyVjfWsE/bzaZp5l1+nWJQBalw47tF3PBUHjtfmb0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LpjuM2eWIlanNalI3CJc65DINl2ciZ4R9WD54awdIJqgcZ5Ueg3vg2qjFHhaZxK3T Q0GTUr5tyj8sqcE5oaWtvMN7DvvKASsxn5YbJ0G7Ax3yzNNbP/2OQ5DPDo/S1NdAoz +oLgvz4Yf2jrBvhTYwh+Pu3hxW7EvCh2Tl2/SfqA= Received: from blr-ubuntu-173.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E3C0A602FC; Wed, 12 Dec 2018 09:25:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1544606735; bh=M/OyVjfWsE/bzaZp5l1+nWJQBalw47tF3PBUHjtfmb0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OvPB/EooTMySkiQrU+acLe7hsVG+xRFXjab1HAKit9MPpbTQUCasrTP9O3qOC8Yn+ 2kWdQoiVnDGLx/1851cmv6csL1l2KVTgIlNSYVfmSxaq6V4BTceo0XJPvePQz5Z9u7 OtJ0tWhw38Lt5BP63IHObAbDIk3FND6kQ8icRTtM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E3C0A602FC Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: andy.gross@linaro.org, robh@kernel.org, viresh.kumar@linaro.org, sboyd@kernel.org, ulf.hansson@linaro.org, collinsd@codeaurora.org, mka@chromium.org Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Rajendra Nayak Subject: [PATCH v7 01/10] dt-bindings: opp: Introduce qcom-opp bindings Date: Wed, 12 Dec 2018 14:51:22 +0530 Message-Id: <20181212092131.13046-2-rnayak@codeaurora.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181212092131.13046-1-rnayak@codeaurora.org> References: <20181212092131.13046-1-rnayak@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Qualcomm Technologies, Inc. platforms, an OPP node needs to describe an additional level/corner value that is then communicated to a remote microprocessor by the CPU, which then takes some actions (like adjusting voltage values across various rails) based on the value passed. Describe these bindings in the qcom-opp bindings document. Signed-off-by: Rajendra Nayak Acked-by: Viresh Kumar Reviewed-by: Stephen Boyd Reviewed-by: Rob Herring --- .../devicetree/bindings/opp/qcom-opp.txt | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/opp/qcom-opp.txt diff --git a/Documentation/devicetree/bindings/opp/qcom-opp.txt b/Documentation/devicetree/bindings/opp/qcom-opp.txt new file mode 100644 index 000000000000..db4d970c7ec7 --- /dev/null +++ b/Documentation/devicetree/bindings/opp/qcom-opp.txt @@ -0,0 +1,25 @@ +Qualcomm OPP bindings to descibe OPP nodes with corner/level values + +OPP tables for devices on Qualcomm platforms require an additional +platform specific corner/level value to be specified. +This value is passed on to the RPM (Resource Power Manager) by +the CPU, which then takes the necessary actions to set a voltage +rail to an appropriate voltage based on the value passed. + +The bindings are based on top of the operating-points-v2 bindings +described in Documentation/devicetree/bindings/opp/opp.txt +Additional properties are described below. + +* OPP Table Node + +Required properties: +- compatible: Allow OPPs to express their compatibility. It should be: + "operating-points-v2-qcom-level" + +* OPP Node + +Required properties: +- qcom,level: On Qualcomm platforms an OPP node can describe a positive value +representing a corner/level that's communicated with a remote microprocessor +(usually called the RPM) which then translates it into a certain voltage on +a voltage rail.