| Message ID | 20181215103557.2748-2-govinds@codeaurora.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add non PAS wcss Q6 support for QCS404 | expand |
Quoting Govind Singh (2018-12-15 02:35:51) > Add device tree bindings for WiFi QDSP subsystem clock controls > found in OCS405 soc. > > Signed-off-by: Govind Singh <govinds@codeaurora.org> > Reviewed-by: Rob Herring <robh@kernel.org> It was? > diff --git a/Documentation/devicetree/bindings/clock/qcom,wcsscc.txt b/Documentation/devicetree/bindings/clock/qcom,wcsscc.txt > new file mode 100644 > index 000000000000..2b19ef0b5689 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,wcsscc.txt > @@ -0,0 +1,26 @@ > +Qualcomm WCSS Clock Controller Binding > +----------------------------------------------- > + > +Required properties : > +- compatible : shall contain "qcom,qcs404-wcsscc" > +- #clock-cells : from common clock binding, shall contain 1. Drop the full-stop please. > +- reg : shall contain base register address and size, > + in the order > + Index-0 maps to WCSS_Q6SSTOP clocks register region > + Index-1 maps to WCSS_TCSR register region > + Index-2 maps to WCSS_QDSP6SS register region > + Index 0, Index 1, Index 2? Not sure why there's a hyphen there. > +Optional properties : > +- reg-names : register names of WCSS domain > + "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss". > + > +Example: > +The below node has to be defined in the cases where the WCSS peripheral loader > +would bring the subsystem out of reset. > + > + clock_wcsscc: qcom,wcsscc@7000000 { clock-controller@7000000 > + compatible = "qcom,qcs404-wcsscc"; > + reg = <0x07500000 0x4e000>, <0x07550000 0x8012>, <0x07400000 0x104>; And then that unit address doesn't match the first offset so that needs fixing too. > + reg-names = "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss"; > + #clock-cells = <1>; > + };
On 2018-12-18 01:03, Stephen Boyd wrote: > Quoting Govind Singh (2018-12-15 02:35:51) >> Add device tree bindings for WiFi QDSP subsystem clock controls >> found in OCS405 soc. > >> +- reg : shall contain base register address and >> size, >> + in the order >> + Index-0 maps to WCSS_Q6SSTOP clocks register >> region >> + Index-1 maps to WCSS_TCSR register region >> + Index-2 maps to WCSS_QDSP6SS register region >> + > > Index 0, Index 1, Index 2? Not sure why there's a hyphen there. > Fixed in v4. >> +Optional properties : >> +- reg-names : register names of WCSS domain >> + "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss". >> + >> +Example: >> +The below node has to be defined in the cases where the WCSS >> peripheral loader >> +would bring the subsystem out of reset. >> + >> + clock_wcsscc: qcom,wcsscc@7000000 { > > clock-controller@7000000 > >> + compatible = "qcom,qcs404-wcsscc"; >> + reg = <0x07500000 0x4e000>, <0x07550000 0x8012>, >> <0x07400000 0x104>; > > And then that unit address doesn't match the first offset so that needs > fixing too. > Fixed in V4. >> + reg-names = "wcss_q6sstop", "wcnss_tcsr", >> "wcss_qdsp6ss"; >> + #clock-cells = <1>; >> + }; BR, Govind
diff --git a/Documentation/devicetree/bindings/clock/qcom,wcsscc.txt b/Documentation/devicetree/bindings/clock/qcom,wcsscc.txt new file mode 100644 index 000000000000..2b19ef0b5689 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,wcsscc.txt @@ -0,0 +1,26 @@ +Qualcomm WCSS Clock Controller Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,qcs404-wcsscc" +- #clock-cells : from common clock binding, shall contain 1. +- reg : shall contain base register address and size, + in the order + Index-0 maps to WCSS_Q6SSTOP clocks register region + Index-1 maps to WCSS_TCSR register region + Index-2 maps to WCSS_QDSP6SS register region + +Optional properties : +- reg-names : register names of WCSS domain + "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss". + +Example: +The below node has to be defined in the cases where the WCSS peripheral loader +would bring the subsystem out of reset. + + clock_wcsscc: qcom,wcsscc@7000000 { + compatible = "qcom,qcs404-wcsscc"; + reg = <0x07500000 0x4e000>, <0x07550000 0x8012>, <0x07400000 0x104>; + reg-names = "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss"; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/qcom,wcss-qcs404.h b/include/dt-bindings/clock/qcom,wcss-qcs404.h new file mode 100644 index 000000000000..45dd6599db81 --- /dev/null +++ b/include/dt-bindings/clock/qcom,wcss-qcs404.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_WCSS_QCS404_H +#define _DT_BINDINGS_CLK_WCSS_QCS404_H + +#define WCSS_AHBFABRIC_CBCR_CLK 0 +#define WCSS_AHBS_CBCR_CLK 1 +#define WCSS_TCM_CBCR_CLK 2 +#define WCSS_AHBM_CBCR_CLK 3 +#define WCSS_AXIM_CBCR_CLK 4 +#define WCSS_BCR_CBCR_CLK 5 +#define WCSS_LCC_CBCR_CLK 6 +#define WCSS_QDSP6SS_XO_CBCR_CLK 7 +#define WCSS_QDSP6SS_SLEEP_CBCR_CLK 8 +#define WCSS_QDSP6SS_GFMMUX_CLK 9 + +#define Q6SSTOP_QDSP6SS_RESET 0 +#define Q6SSTOP_QDSP6SS_CORE_RESET 1 +#define Q6SSTOP_QDSP6SS_BUS_RESET 2 +#define Q6SSTOP_BCR_RESET 3 +#endif