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[2/2] clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock

Message ID 20190128115359.30039-2-vkoul@kernel.org (mailing list archive)
State New, archived
Headers show
Series [1/2] clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs | expand

Commit Message

Vinod Koul Jan. 28, 2019, 11:53 a.m. UTC 
From: Taniya Das <tdas@codeaurora.org>

The CFG/M/N/D registers are at an offset of 0x20 from the CMD register
for blsp1_uart3 clock, so add it.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/clk/qcom/gcc-qcs404.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Stephen Boyd Jan. 29, 2019, 10:42 p.m. UTC | #1 
Quoting Vinod Koul (2019-01-28 03:53:59)
> diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
> index 64da032bb9ed..493e055299b4 100644
> --- a/drivers/clk/qcom/gcc-qcs404.c
> +++ b/drivers/clk/qcom/gcc-qcs404.c
> @@ -678,6 +678,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
>         .cmd_rcgr = 0x4014,
>         .mnd_width = 16,
>         .hid_width = 5,
> +       .cfg_off = 0x20,

And it's one single clk! None of the other blsp clks have this problem?

>         .parent_map = gcc_parent_map_0,
>         .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
>         .clkr.hw.init = &(struct clk_init_data){
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 64da032bb9ed..493e055299b4 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -678,6 +678,7 @@  static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 	.cmd_rcgr = 0x4014,
 	.mnd_width = 16,
 	.hid_width = 5,
+	.cfg_off = 0x20,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){