From patchwork Wed Jan 30 11:04:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 10788285 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 99D921390 for ; Wed, 30 Jan 2019 11:04:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 874242D045 for ; Wed, 30 Jan 2019 11:04:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7B1622D34C; Wed, 30 Jan 2019 11:04:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 18F062D045 for ; Wed, 30 Jan 2019 11:04:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730677AbfA3LEs (ORCPT ); Wed, 30 Jan 2019 06:04:48 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:41609 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730572AbfA3LEs (ORCPT ); Wed, 30 Jan 2019 06:04:48 -0500 Received: by mail-wr1-f66.google.com with SMTP id x10so25505931wrs.8 for ; Wed, 30 Jan 2019 03:04:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EqtbkSQo7L/mANhknVJMLP+N/PdTpbVp8wiFd5sS1F4=; b=diXVS6PJBdiMcOYaOG/ZY3fIgtF55Dr3OKVSfizpuVp2CdlATsN2/QrFRWWbwOktBB wCJKa3koHcTuAcZJ/xzTco+eZzHXPuR4/yfce2YskejIieKZHsCITJezxzpTdu+uphwm xZJnBB84S3ka3smS+BTvqC6yRdhucpjr+226M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EqtbkSQo7L/mANhknVJMLP+N/PdTpbVp8wiFd5sS1F4=; b=RG2QYxJ2EEEhnAnhiNxAMMai71Fkun3FqdxHcDLdh9kwISHvY5T/ihbb95/mze/AeT G9In7iLjtN3pGxOwl2cGJRs957BKsebQfZ0DQswuxPJfm1Ixulqjm2GQfBaZ2wuq1WZ2 PBu/ybFJQKC9n7uiNvmJZezI3jeIQlh8ngXDz//2DpuQj9YNEOXwCTCmBBrPEVIwh9+p 0cw74a4zu43J+2KCckDVeVlYTs/ii0NFTcYXWLyq6DK0zNqu/q7NYIAuhinwQHQC93tg iyqGAsc+EZASE7QZ8ltutNWGVnxsGxgcmvau+nbMhozbcxDPAOnd/Z2165SaXkYrHTFC Jnjg== X-Gm-Message-State: AJcUukdXBCCBmSV14jOGw0jAO4frE5CiVTq+tJXj5089Cp6QbMNcRR3E Kb2aGY/yHg7UKMBymdrJfZE0jA== X-Google-Smtp-Source: ALg8bN69ecBVATvgzM0eUK+4q6/ufUQGsgWiXf3HdmFnIWINbcGdnFoTrg3MIEq2EEn48xs3pBoFwQ== X-Received: by 2002:adf:c108:: with SMTP id r8mr30891283wre.233.1548846286387; Wed, 30 Jan 2019 03:04:46 -0800 (PST) Received: from srini-hackbox.lan (cpc89974-aztw32-2-0-cust43.18-1.cable.virginm.net. [86.30.250.44]) by smtp.gmail.com with ESMTPSA id w16sm1138208wrp.1.2019.01.30.03.04.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 Jan 2019 03:04:45 -0800 (PST) From: Srinivas Kandagatla To: andy.gross@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Jordan Crouse , Vivek Gautam , Srinivas Kandagatla Subject: [PATCH v2 4/6] arm64: dts: Add Adreno GPU definitions Date: Wed, 30 Jan 2019 11:04:35 +0000 Message-Id: <20190130110437.5424-5-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190130110437.5424-1-srinivas.kandagatla@linaro.org> References: <20190130110437.5424-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jordan Crouse Add an initial node for the Adreno GPU. Signed-off-by: Vivek Gautam Signed-off-by: Srinivas Kandagatla Signed-off-by: Jordan Crouse --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 86 +++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 0d0b9482aa4d..095041589954 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -84,6 +84,12 @@ qcom,client-id = <1>; qcom,vmid = <15>; }; + + zap_shader_region: gpu@8f200000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x90b00000 0x0 0xa00000>; + no-map; + }; }; cpus { @@ -796,6 +802,11 @@ reg = <0x24f 0x1>; bits = <1 4>; }; + + gpu_speed_bin: gpu_speed_bin@133 { + reg = <0x133 0x1>; + bits = <5 3>; + }; }; phy@34000 { @@ -1338,6 +1349,81 @@ }; }; + gpu@b00000 { + compatible = "qcom,adreno-530.2", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0xb00000 0x3f000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mmcc GPU_GX_GFX3D_CLK>, + <&mmcc GPU_AHB_CLK>, + <&mmcc GPU_GX_RBBMTIMER_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_MMSS_BIMC_GFX_CLK>; + + clock-names = "core", + "iface", + "rbbmtimer", + "mem", + "mem_iface"; + + power-domains = <&mmcc GPU_GDSC>; + iommus = <&adreno_smmu 0>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + qcom,gpu-quirk-two-pass-use-wfi; + qcom,gpu-quirk-fault-detect-mask; + + operating-points-v2 = <&gpu_opp_table>; + + gpu_opp_table: opp-table { + compatible ="operating-points-v2"; + + /* + * 624Mhz and 560Mhz are only available on speed + * bin (1 << 0). All the rest are available on + * all bins of the hardware + */ + opp-624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-supported-hw = <0x01>; + }; + opp-560000000 { + opp-hz = /bits/ 64 <560000000>; + opp-supported-hw = <0x01>; + }; + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + opp-supported-hw = <0xFF>; + }; + opp-401800000 { + opp-hz = /bits/ 64 <401800000>; + opp-supported-hw = <0xFF>; + }; + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-supported-hw = <0xFF>; + }; + opp-214000000 { + opp-hz = /bits/ 64 <214000000>; + opp-supported-hw = <0xFF>; + }; + opp-133000000 { + opp-hz = /bits/ 64 <133000000>; + opp-supported-hw = <0xFF>; + }; + }; + + zap-shader { + memory-region = <&zap_shader_region>; + }; + }; + mdss: mdss@900000 { compatible = "qcom,mdss";