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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id 15sm1007622pfs.113.2019.01.30.16.00.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Jan 2019 16:00:21 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Escande , Srinivas Kandagatla Subject: [PATCH] arm64: dts: qcom: qcs404: Define APPS IOMMU Date: Wed, 30 Jan 2019 16:00:06 -0800 Message-Id: <20190131000006.11145-1-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The APPS IOMMU provides contexts for FastRPC, MDP and WLAN, among other things. Define these. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 85 ++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index d90decd00f5c..c574e48c61d2 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -395,6 +395,91 @@ reg = <0x01905000 0x20000>; }; + apps_iommu: iommu@1e20000 { + compatible = "qcom,qcs404-iommu", "qcom,msm-iommu-v1"; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <17>; + + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + + /* Define ranges such that the first bank is at 0x1000 */ + ranges = <0 0x01e20000 0x40000>; + + /* Bank 5: CDSP compute bank 1 */ + iommu-ctx@5000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x5000 0x1000>; + interrupts = ; + }; + + /* Bank 6: CDSP compute bank 2 */ + iommu-ctx@6000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x6000 0x1000>; + interrupts = ; + }; + + /* Bank 7: CDSP compute bank 3 */ + iommu-ctx@7000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x7000 0x1000>; + interrupts = ; + }; + + /* Bank 8: CDSP compute bank 4 */ + iommu-ctx@8000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x8000 0x1000>; + interrupts = ; + }; + + /* Bank 9: CDSP compute bank 5 */ + iommu-ctx@9000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x9000 0x1000>; + interrupts = ; + }; + + /* Bank 10: MDP */ + iommu-ctx@a000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0xa000 0x1000>; + interrupts = ; + }; + + /* Bank 21: WLAN 0 */ + iommu-ctx@15000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x15000 0x1000>; + interrupts = ; + }; + + /* Bank 23: ADSP compute bank 2 */ + iommu-ctx@17000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x17000 0x1000>; + interrupts = ; + }; + + /* Bank 24: ADSP compute bank 3 */ + iommu-ctx@18000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x18000 0x1000>; + interrupts = ; + }; + + /* Bank 25: ADSP compute bank 4 */ + iommu-ctx@19000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x19000 0x1000>; + interrupts = ; + }; + }; + spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0200f000 0x001000>,