| Message ID | 20190921100439.64402-2-kholk11@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | DRM/MSM: Add support for MSM8956 and Adreno 510 | expand |
On Sun, Sep 22, 2019 at 8:16 AM <kholk11@gmail.com> wrote: > > From: "Angelo G. Del Regno" <kholk11@gmail.com> > > Some SoCs, like MSM8956/8976 (and APQ variants), do feature these > clocks and we need to enable them in order to get the hardware to > properly work. > > Signed-off-by: Angelo G. Del Regno <kholk11@gmail.com> I don't see these clocks documented in the mdp5 DT bindings document. They need to be added in the DT first.
Il giorno lun 23 set 2019 alle ore 02:45 Jeffrey Hugo <jeffrey.l.hugo@gmail.com> ha scritto: > > On Sun, Sep 22, 2019 at 8:16 AM <kholk11@gmail.com> wrote: > > > > From: "Angelo G. Del Regno" <kholk11@gmail.com> > > > > Some SoCs, like MSM8956/8976 (and APQ variants), do feature these > > clocks and we need to enable them in order to get the hardware to > > properly work. > > > > Signed-off-by: Angelo G. Del Regno <kholk11@gmail.com> > > I don't see these clocks documented in the mdp5 DT bindings document. > They need to be added in the DT first. I know, you're right... I've just noticed it. I'm sorry, I've completely forgotten to add them to the documentation. I'll do that ASAP and resend.
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c index fec6ef1ae3b9..23be9b95dd7e 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -293,6 +293,10 @@ int mdp5_disable(struct mdp5_kms *mdp5_kms) mdp5_kms->enable_count--; WARN_ON(mdp5_kms->enable_count < 0); + if (mdp5_kms->tbu_rt_clk) + clk_disable_unprepare(mdp5_kms->tbu_rt_clk); + if (mdp5_kms->tbu_clk) + clk_disable_unprepare(mdp5_kms->tbu_clk); clk_disable_unprepare(mdp5_kms->ahb_clk); clk_disable_unprepare(mdp5_kms->axi_clk); clk_disable_unprepare(mdp5_kms->core_clk); @@ -313,6 +317,10 @@ int mdp5_enable(struct mdp5_kms *mdp5_kms) clk_prepare_enable(mdp5_kms->core_clk); if (mdp5_kms->lut_clk) clk_prepare_enable(mdp5_kms->lut_clk); + if (mdp5_kms->tbu_clk) + clk_prepare_enable(mdp5_kms->tbu_clk); + if (mdp5_kms->tbu_rt_clk) + clk_prepare_enable(mdp5_kms->tbu_rt_clk); return 0; } @@ -948,6 +956,8 @@ static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) /* optional clocks: */ get_clk(pdev, &mdp5_kms->lut_clk, "lut", false); + get_clk(pdev, &mdp5_kms->tbu_clk, "tbu", false); + get_clk(pdev, &mdp5_kms->tbu_rt_clk, "tbu_rt", false); /* we need to set a default rate before enabling. Set a safe * rate first, then figure out hw revision, and then set a diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h index d1bf4fdfc815..128866742593 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h @@ -53,6 +53,8 @@ struct mdp5_kms { struct clk *ahb_clk; struct clk *core_clk; struct clk *lut_clk; + struct clk *tbu_clk; + struct clk *tbu_rt_clk; struct clk *vsync_clk; /*