From patchwork Wed Nov 6 08:46:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 11229667 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 081051575 for ; Wed, 6 Nov 2019 08:47:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D8DA8217F4 for ; Wed, 6 Nov 2019 08:47:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1573030045; bh=QlCZGgwKxaEkTEzsEFbie7EjDl/Pz20nyu4/Pp/JumM=; h=From:To:Cc:Subject:Date:List-ID:From; b=x0YW8VBrWE+P+l6JCqjQ9ZfpnwpXeICyy4P/T82ue1l9zcsZ8Zet2S+VB8xZDZJYX nsizwOwnoDsc2THaOWWL35PewyuLn9QdMyfJcIWjLf7M08vPIaQ92PnhUIO0Z/3PqY Le2UfFObX1Uo6m8CdLywDJ58p0ZX7UE4708rDCFU= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730069AbfKFIrS (ORCPT ); Wed, 6 Nov 2019 03:47:18 -0500 Received: from mail.kernel.org ([198.145.29.99]:51014 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730178AbfKFIrS (ORCPT ); Wed, 6 Nov 2019 03:47:18 -0500 Received: from localhost.localdomain (unknown [223.226.46.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 91760206A3; Wed, 6 Nov 2019 08:47:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1573030037; bh=QlCZGgwKxaEkTEzsEFbie7EjDl/Pz20nyu4/Pp/JumM=; h=From:To:Cc:Subject:Date:From; b=BY5Q1Ag499IbAp9AaGG5mXDG5zDwEjKKg/VGn4SkrWrPANK7Admo3WU8LtFwGxVQp snt37EjOkqY2RmA9c6OeJsMeGFYF0456g61JHzTkOnca+CyOUCHRDNg9Enn609wMsZ Rto/clU6de/OqjaCN2D8ZxjoYBgExcM9Bnp/qA4M= From: Vinod Koul To: Andy Gross Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] arm64: dts: qcom: sm8150: Add ufs nodes Date: Wed, 6 Nov 2019 14:16:55 +0530 Message-Id: <20191106084656.1749954-1-vkoul@kernel.org> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the ufs hc node and ufs phy nodes found in SM8150 Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 68 ++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a9b1cabccbf6..f36d621a53e2 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -508,6 +508,74 @@ }; }; + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sm8150-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x2500>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <37500000 300000000>, + <0 0>, + <0 0>, + <37500000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sm8150-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x18c>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: lanes@1d87400 { + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x108>, + <0 0x01d87a00 0 0x1e0>; + #phy-cells = <0>; + }; + }; + tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; reg = <0x0 0x01f40000 0x0 0x40000>;