From patchwork Mon Dec 30 14:44:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 11313213 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CB23A109A for ; Mon, 30 Dec 2019 14:44:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A937B20722 for ; Mon, 30 Dec 2019 14:44:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="s5zzc4Lz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727615AbfL3Oof (ORCPT ); Mon, 30 Dec 2019 09:44:35 -0500 Received: from mail-lj1-f194.google.com ([209.85.208.194]:37953 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727630AbfL3Oof (ORCPT ); Mon, 30 Dec 2019 09:44:35 -0500 Received: by mail-lj1-f194.google.com with SMTP id w1so11532472ljh.5 for ; Mon, 30 Dec 2019 06:44:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pFHyotJ6IeS0NnPGUwSrCQs8d27XE2yrJ5nxr3VtYic=; b=s5zzc4Lzvw9BL4eBPMqCkzI1609Ctjtx+HMMegsZzrLbvJR3PQGlrle85pbQIAjvQv spD0gMVv3McQxNFa9n7sHSB0CtaQvF20UZS6K5kWhrw/1n0QclJEHvtiB5eSVvJ3yfWG lTg1kc+5OHIy3eladTvA82JxUYopI+/UzQCz8HJiivLaVAl3CPevey+/gcyxcbXuu4lo Ae882oP6a3qVoJHFFKttCYL4xHchd0e9DRbh+BmiqVAJGnXrXoajVof6Mep88AChD8nP bMhjSjVl8YnbU5WlaYGRh8onvQMHN7Gi3m37K1wv4IZidNEBKaAgQzZaK9dNoDXCyQtA EXtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pFHyotJ6IeS0NnPGUwSrCQs8d27XE2yrJ5nxr3VtYic=; b=GpdXRvLTFwhFq8BMwK541U92FPclUTFzvv+KoZBpDJOnH7Aoslo0eBi+SmJsBuSOPH CQ0SJ2Mpx3i8Bp+ZWR+Kp6Z+zfgJB8B2cGylxeGsP+1edyayeaTfr6WzSp/2MS65Ch/C v9l+aRMTTUQ404E0Xyj+WavFZAziLESDZBFCndgTIC/bZ4tmyYgDeIcmNy/r0XqnBbzP 9FfBkLNTkxYJQTru5eBATsTlzhzXgIh+k+kOfbXvOdbdaNon7pS5PotsLdhTOoe9QUEn zLCnenfvfmeO/lhVABx+4i9Lp4m2u24Xv1zQaPq3ysvi1nzKVMd0EndzFA+RbRO4dGFz s5zA== X-Gm-Message-State: APjAAAX1StyrpnGQq2GKRa9kJiLNG/Z+Z8L9HAyx4Izx4zQFVVI9nSGx BlkBiktSbV2Ka1PPmY/9n4zVaQ== X-Google-Smtp-Source: APXvYqxdwGv5e3gJirom9yUfoCDD87334k/2EA5omu7hFVl0AB/wYbg/vlbug4VqdBA+bheY1tQrbA== X-Received: by 2002:a2e:9a01:: with SMTP id o1mr37050340lji.247.1577717072600; Mon, 30 Dec 2019 06:44:32 -0800 (PST) Received: from localhost.localdomain (h-158-174-22-210.NA.cust.bahnhof.se. [158.174.22.210]) by smtp.gmail.com with ESMTPSA id a21sm18744931lfg.44.2019.12.30.06.44.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Dec 2019 06:44:32 -0800 (PST) From: Ulf Hansson To: Sudeep Holla , Lorenzo Pieralisi , Rob Herring , linux-pm@vger.kernel.org Cc: "Rafael J . Wysocki" , Daniel Lezcano , Mark Rutland , Lina Iyer , Vincent Guittot , Stephen Boyd , Andy Gross , Bjorn Andersson , Kevin Hilman , Ulf Hansson , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Lina Iyer Subject: [PATCH v5 15/15] arm64: dts: Convert to the hierarchical CPU topology layout for MSM8916 Date: Mon, 30 Dec 2019 15:44:02 +0100 Message-Id: <20191230144402.30195-16-ulf.hansson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191230144402.30195-1-ulf.hansson@linaro.org> References: <20191230144402.30195-1-ulf.hansson@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org To enable the OS to better support PSCI OS initiated CPU suspend mode, let's convert from the flattened layout to the hierarchical layout. In the hierarchical layout, let's create a power domain provider per CPU and describe the idle states for each CPU inside the power domain provider node. To group the CPUs into a cluster, let's add another power domain provider and make it act as the master domain. Note that, the CPU's idle states remains compatible with "arm,idle-state", while the cluster's idle state becomes compatible with "domain-idle-state". Co-developed-by: Lina Iyer Signed-off-by: Lina Iyer Signed-off-by: Ulf Hansson Reviewed-by: Sudeep Holla --- Changes in v5: - None. --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 57 +++++++++++++++++++++++++-- 1 file changed, 53 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 8686e101905c..282c36c8fa3b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -102,10 +102,11 @@ reg = <0x0>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; }; CPU1: cpu@1 { @@ -114,10 +115,11 @@ reg = <0x1>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; }; CPU2: cpu@2 { @@ -126,10 +128,11 @@ reg = <0x2>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; }; CPU3: cpu@3 { @@ -138,10 +141,11 @@ reg = <0x3>; next-level-cache = <&L2_0>; enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; }; L2_0: l2-cache { @@ -161,12 +165,57 @@ min-residency-us = <2000>; local-timer-stop; }; + + CLUSTER_RET: cluster-retention { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000012>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWRDN: cluster-gdhs { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000032>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP_0>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP_0>; + }; + + CPU_PD2: cpu-pd2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP_0>; + }; + + CPU_PD3: cpu-pd3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP_0>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; + }; }; pmu {