From patchwork Mon Dec 30 16:43:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11313473 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EA952139A for ; Mon, 30 Dec 2019 16:43:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C955720718 for ; Mon, 30 Dec 2019 16:43:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Ue9Dh2bN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727175AbfL3QnQ (ORCPT ); Mon, 30 Dec 2019 11:43:16 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:43357 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727146AbfL3QnQ (ORCPT ); Mon, 30 Dec 2019 11:43:16 -0500 Received: by mail-wr1-f66.google.com with SMTP id d16so33162212wre.10 for ; Mon, 30 Dec 2019 08:43:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YB3f30pJRu3JULH7XG/mWzUNFJ0TPVlsc2Y5J8rGS1s=; b=Ue9Dh2bNnHoL9o8EcVY3qR9lIVVycoMC1u1NtH9SFNUioxB6SkJz3IKPMgaCQ/UAkt 0vMGRXrHWGGj2mRu9BhayYSw4X2/dkWxRAvSMi8vfzZpFyPBdLq3+Lkxlke1j/apaCN5 3YTqtO94MKtRyOAY00LlN6rok4TvaCzWCMRjuh99uUmQmWhucbhqQ2mRUoAzIWkeFN7f r+GLhAcRUhSSXY51YjweNm7dFxMnIEWm+9t3t60t8PDJRJhgjEkoT3idhOoP753tQWCJ IfI947cQ3mzLdkwDy0YYQa39vg8GFJ8zDshhST0tF8ICm8khyPlHC5dpi4TB1lv5/rff 1J/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YB3f30pJRu3JULH7XG/mWzUNFJ0TPVlsc2Y5J8rGS1s=; b=TWmryb2GOvCzwOL6yEnFZCDvcTB6JfLevXEemmukhCt3KAqwDq54Us6q9tT6+6VwUu 2RnfmGCNltBAAxnZGNjinmET6kDGB2rVGSI5yyb8mv2Dp3oZHTcerq2dCUkuSE5NOiI+ BGZMImSZ5351zuKSFbnEEJzMgcqY5tTa+gnP57ENK/GygK6UG4WOJMzhOZw0XL9IKUXb vCfZc12opt2SF6XRGKKtBYqNlQrdu7QL46+zCWvHUgOTSny2T9IPGe6TwXdiTAKKt2dg bjwpYzXC6RudswxXTm3tNMv1CJWyN/CHAEWfGcGiyJ47JsKYbCacohH9Oe1gBKzrJ/hS c2rA== X-Gm-Message-State: APjAAAU6ALijrYRXBEjsaeWAXpjfXv0giKVGbojGaDWUEnwHex29JAtg Kf0AcAXWaA/wiuCbfT1lA/KC//YMA3Br8g== X-Google-Smtp-Source: APXvYqyditLM4czt6DXltQROybhVhYPGdF3xp/LxygA3E4yhhkZTRYqMwvzcOg1NkjI3oh5TgzYlTg== X-Received: by 2002:adf:f58a:: with SMTP id f10mr70947710wro.105.1577724193953; Mon, 30 Dec 2019 08:43:13 -0800 (PST) Received: from linaro.org ([2a00:23c5:6815:3901:a1cf:b00b:5683:ed40]) by smtp.gmail.com with ESMTPSA id g25sm344901wmh.3.2019.12.30.08.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Dec 2019 08:43:13 -0800 (PST) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, coresight@lists.linaro.org Cc: linux-arm-msm@vger.kernel.org, mathieu.poirier@linaro.org, suzuki.poulose@arm.com, robh+dt@kernel.org, maxime@cerno.tech, liviu.dudau@arm.com, sudeep.holla@arm.com, lorenzo.pieralisi@arm.com, agross@kernel.org, Mike Leach Subject: [PATCH v7 10/15] dt-bindings: qcom: Add CTI options for qcom msm8916 Date: Mon, 30 Dec 2019 16:43:06 +0000 Message-Id: <20191230164306.28259-2-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191230164306.28259-1-mike.leach@linaro.org> References: <20191230164306.28259-1-mike.leach@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Adds system and CPU bound CTI definitions for Qualcom msm8916 platform (Dragonboard DB410C). System CTIs 2-11 are omitted as no information available at present. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier Acked-by: Suzuki K Poulose --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 85 +++++++++++++++++++++++++-- 1 file changed, 81 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 8686e101905c..68587968f5c0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -1357,7 +1358,7 @@ cpu = <&CPU3>; }; - etm@85c000 { + etm0: etm@85c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85c000 0x1000>; @@ -1375,7 +1376,7 @@ }; }; - etm@85d000 { + etm1: etm@85d000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85d000 0x1000>; @@ -1393,7 +1394,7 @@ }; }; - etm@85e000 { + etm2: etm@85e000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85e000 0x1000>; @@ -1411,7 +1412,7 @@ }; }; - etm@85f000 { + etm3: etm@85f000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85f000 0x1000>; @@ -1429,6 +1430,82 @@ }; }; + /* System CTIs */ + /* CTI 0 - TMC connections */ + cti@810000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x810000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + /* CTI 1 - TPIU connections */ + cti@811000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x811000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + /* CTIs 2-11 - no information - not instantiated */ + + /* Core CTIs; CTIs 12-15 */ + /* CTI - CPU-0 */ + cti@858000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x858000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU0>; + arm,cs-dev-assoc = <&etm0>; + + }; + + /* CTI - CPU-1 */ + cti@859000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x859000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + arm,cs-dev-assoc = <&etm1>; + }; + + /* CTI - CPU-2 */ + cti@85a000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x85a000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU2>; + arm,cs-dev-assoc = <&etm2>; + }; + + /* CTI - CPU-3 */ + cti@85b000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x85b000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU3>; + arm,cs-dev-assoc = <&etm3>; + }; + + venus: video-codec@1d00000 { compatible = "qcom,msm8916-venus"; reg = <0x01d00000 0xff000>;