From patchwork Mon Dec 30 16:43:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11313481 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 015E0139A for ; Mon, 30 Dec 2019 16:43:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D3BD220730 for ; Mon, 30 Dec 2019 16:43:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="SBzZ0rDZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727104AbfL3Qnu (ORCPT ); Mon, 30 Dec 2019 11:43:50 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:40866 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727146AbfL3Qnu (ORCPT ); Mon, 30 Dec 2019 11:43:50 -0500 Received: by mail-wr1-f66.google.com with SMTP id c14so33155586wrn.7 for ; Mon, 30 Dec 2019 08:43:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BucIs76BJlau9NCsGrtA8TwA9hcR+pRMGii5xstBwn8=; b=SBzZ0rDZRjiKBsb2L/NpX+zIZ1gIR5WsGJdHWgR0Or+ZErpG5vx0saPuQCq2dF7Y5r UmjrJarGEPj+GT5o/z9Jq6OFGg9WRY/8qzrTxIDzwWi6bVGLVZDdZSdjBpOlKx13JHxd wLH3pptL74jNCfSy+FDsi2YSMXwCuDAnWvdVAHC4jAQl0Q1cHAUAXk4Pgxb3oDik8VTR J2ad3GoGnPCrI4tR4bfELh9X06NhXvNDQ7c7TGt/uCKyeFi2cH1MdoV6sKTswfBnfAWF 5/n3YPjt5fbb1XiAN3slTk5NlHoA7Rc5NMt76N6zbDNB+We1AUI8hS58f8kR7/CdR1eE A0pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BucIs76BJlau9NCsGrtA8TwA9hcR+pRMGii5xstBwn8=; b=crCle3yRrbdShZTN8wLrKCeYQNYLs3L3HZHcHykcwo7Ytl4+HoGwuk6oT9bYCZKnLs UK032J88I68PGkZqPzg7aygIq0bs4ULvVPI1BCUFca6lP9RUj+ro+84OkfkqZZmblkHd r3U8zO5rxszVDsT/E0MOyWj7OIjPg7Nhqlz37ocTnDbf8G3Pkn9xfUAagtGzBoUTDwIj yICjuO7orq7PDZjsUYn8Sw8gRRH3h/3B6BgEcPwmbgSPOQurcqjRlJObdlt+UOAHmG4u q0676hH1p69ZSd/BAPFnWTl2bDiP8EVXVlPF0IpLyf37VRDHZjPTs3KeLsbSOer0wroF XU9A== X-Gm-Message-State: APjAAAWn7dyOmhiDpvM42bgv55JsvYLWXj6/vYDhd/q6XWi9NMSTA7Pt v4H1+NGClrSfyFvxAvw1LLeDmg== X-Google-Smtp-Source: APXvYqxsnvEw9WLsPaciInH5I+ri43dDgiWBaydmGgYdjUWTk+gcvQO8oEURiJMLKo3qtystWutxpQ== X-Received: by 2002:a5d:6a0f:: with SMTP id m15mr67691513wru.40.1577724227316; Mon, 30 Dec 2019 08:43:47 -0800 (PST) Received: from linaro.org ([2a00:23c5:6815:3901:a1cf:b00b:5683:ed40]) by smtp.gmail.com with ESMTPSA id g2sm45691586wrw.76.2019.12.30.08.43.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Dec 2019 08:43:46 -0800 (PST) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, coresight@lists.linaro.org Cc: linux-arm-msm@vger.kernel.org, mathieu.poirier@linaro.org, suzuki.poulose@arm.com, robh+dt@kernel.org, maxime@cerno.tech, liviu.dudau@arm.com, sudeep.holla@arm.com, lorenzo.pieralisi@arm.com, agross@kernel.org, Mike Leach Subject: [PATCH v7 12/15] dt-bindings: hisilicon: Add CTI bindings for hi-6220 Date: Mon, 30 Dec 2019 16:43:40 +0000 Message-Id: <20191230164340.28317-2-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191230164340.28317-1-mike.leach@linaro.org> References: <20191230164340.28317-1-mike.leach@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Adds in CTI device tree information for the Hikey620 board. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier Tested-by: Leo Yan --- .../boot/dts/hisilicon/hi6220-coresight.dtsi | 130 ++++++++++++++++-- 1 file changed, 122 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi index 651771a73ed6..27f067e87601 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi @@ -213,7 +213,7 @@ }; }; - etm@f659c000 { + etm0: etm@f659c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659c000 0 0x1000>; @@ -232,7 +232,7 @@ }; }; - etm@f659d000 { + etm1: etm@f659d000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659d000 0 0x1000>; @@ -251,7 +251,7 @@ }; }; - etm@f659e000 { + etm2: etm@f659e000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659e000 0 0x1000>; @@ -270,7 +270,7 @@ }; }; - etm@f659f000 { + etm3: etm@f659f000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659f000 0 0x1000>; @@ -289,7 +289,7 @@ }; }; - etm@f65dc000 { + etm4: etm@f65dc000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65dc000 0 0x1000>; @@ -308,7 +308,7 @@ }; }; - etm@f65dd000 { + etm5: etm@f65dd000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65dd000 0 0x1000>; @@ -327,7 +327,7 @@ }; }; - etm@f65de000 { + etm6: etm@f65de000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65de000 0 0x1000>; @@ -346,7 +346,7 @@ }; }; - etm@f65df000 { + etm7: etm@f65df000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65df000 0 0x1000>; @@ -364,5 +364,119 @@ }; }; }; + + /* System CTIs */ + /* CTI 0 - TMC and TPIU connections */ + cti@f6403000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0xf6403000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + }; + + /* CTI - CPU-0 */ + cti@f6598000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf6598000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu0>; + arm,cs-dev-assoc = <&etm0>; + }; + + /* CTI - CPU-1 */ + cti@f6599000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf6599000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu1>; + arm,cs-dev-assoc = <&etm1>; + }; + + /* CTI - CPU-2 */ + cti@f659a000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf659a000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu2>; + arm,cs-dev-assoc = <&etm2>; + }; + + /* CTI - CPU-3 */ + cti@f659b000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf659b000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu3>; + arm,cs-dev-assoc = <&etm3>; + }; + + /* CTI - CPU-4 */ + cti@f65d8000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf65d8000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu4>; + arm,cs-dev-assoc = <&etm4>; + }; + + /* CTI - CPU-5 */ + cti@f65d9000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf65d9000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu5>; + arm,cs-dev-assoc = <&etm5>; + }; + + /* CTI - CPU-6 */ + cti@f65da000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf65da000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu6>; + arm,cs-dev-assoc = <&etm6>; + }; + + /* CTI - CPU-7 */ + cti@f65db000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0xf65db000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu7>; + arm,cs-dev-assoc = <&etm7>; + }; }; };