| Message ID | 20200127082331.1.I402470e4a162d69fde47ee2ea708b15bde9751f9@changeid (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | f8c848134185ffcf8409a8b6398c16584c752a1a |
| Headers | show |
| Series | arm64: dts: qcom: qcs404: Fix sdhci compat string | expand |
On 27-01-20, 08:23, Douglas Anderson wrote: > As per the bindings, the SDHCI controller should have a SoC-specific > compatible string in addition to the generic version-based one. Add > it. Thanks for spotting it Doug, Btw did some script catch it or manual inspection? Reviewed-by: Vinod Koul <vkoul@kernel.org> > Fixes: 7241ab944da3 ("arm64: dts: qcom: qcs404: Add sdcc1 node") > Signed-off-by: Douglas Anderson <dianders@chromium.org> > --- > > arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi > index 4ee1e3d5f123..1eea06435779 100644 > --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi > @@ -685,7 +685,7 @@ pcie_phy: phy@7786000 { > }; > > sdcc1: sdcc@7804000 { > - compatible = "qcom,sdhci-msm-v5"; > + compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; > reg = <0x07804000 0x1000>, <0x7805000 0x1000>; > reg-names = "hc_mem", "cmdq_mem"; > > -- > 2.25.0.341.g760bfbb309-goog
Hi, On Mon, Jan 27, 2020 at 9:05 AM Vinod Koul <vkoul@kernel.org> wrote: > > On 27-01-20, 08:23, Douglas Anderson wrote: > > As per the bindings, the SDHCI controller should have a SoC-specific > > compatible string in addition to the generic version-based one. Add > > it. > > Thanks for spotting it Doug, Btw did some script catch it or manual > inspection? > > > Reviewed-by: Vinod Koul <vkoul@kernel.org> It probably would have been spotted by "make dtbs_check", but I wasn't running that in this case. I just happened to notice it while chatting with someone at Qualcomm about whether <https://crrev.com/c/2022985> was correct (still waiting for a response on that). -Doug
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 4ee1e3d5f123..1eea06435779 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -685,7 +685,7 @@ pcie_phy: phy@7786000 { }; sdcc1: sdcc@7804000 { - compatible = "qcom,sdhci-msm-v5"; + compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x7805000 0x1000>; reg-names = "hc_mem", "cmdq_mem";
As per the bindings, the SDHCI controller should have a SoC-specific compatible string in addition to the generic version-based one. Add it. Fixes: 7241ab944da3 ("arm64: dts: qcom: qcs404: Add sdcc1 node") Signed-off-by: Douglas Anderson <dianders@chromium.org> --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)