From patchwork Tue Feb 25 23:46:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Leach X-Patchwork-Id: 11404969 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4C92617D5 for ; Tue, 25 Feb 2020 23:46:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2B27421D7E for ; Tue, 25 Feb 2020 23:46:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="BVDQ4C/j" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729580AbgBYXqs (ORCPT ); Tue, 25 Feb 2020 18:46:48 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:51077 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729595AbgBYXqs (ORCPT ); Tue, 25 Feb 2020 18:46:48 -0500 Received: by mail-wm1-f68.google.com with SMTP id a5so1073187wmb.0 for ; Tue, 25 Feb 2020 15:46:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=C1WY7m7LZykVt5uJs3pBqs/4NQKr7Ot6cOn9UjLkSJM=; b=BVDQ4C/jc/Pi/GKzSD13nQmRjO8HeGX+aflCA1KgwjNFyVjpjDIv5UflF52DFsWq1/ NDOz5gjxMrsxX9IBV+cqvew/3ZSPbPtKebTLsk9WSRCflDfc15InF0JDq0356hYv8k5z QtOwDSntDwnGv7DS+TMaopRA4TPrvMZkRLg7h1TGwii1xrl/RpAFSdAbs4+YFExicRUB GJ72d5vzQomUVzkGZ/HkHvCqzOfyBWyqg4u3nz7KU144qUkfwZsuW1lqkh9MbR+CYFl2 m8MitwlgbsBk9dubF3gBtadtqm0jYBgGtvG96zaQ435AyRB70Q7eFn1SkbX9k7SY+yLe 2bAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=C1WY7m7LZykVt5uJs3pBqs/4NQKr7Ot6cOn9UjLkSJM=; b=l/Nz3+EO1ZVSbR3khJv9608NoQ7UXj2+AhIJramngGezX2+mps9prw59y5+j1Mhsfr /q7gyLkmeEtniDRoEvJYmUdju3thfXyEacar3loSxSsS8zvF8OXII9BguxNSLMsD/Gee gt0MKKVboh3AcknjlJwd4CIwkP/x29MbW7ai24dmV/uDSUta1BSQbA0UxO3Ry9aLSTg0 us+oV9CYmhsFyTV8rCOhM5ymVj2yB1lB5LIgHds6Fpvl9QluzkwQOfgEqd4BQamTZ6le t5Bhz8+i3Rd0kY0UHGLmSd7vfCMDuH0H+QadywMoEXN36mqlzFzo/nfC+ywSHA0kp/sE tBIg== X-Gm-Message-State: APjAAAXQlA2fNSMUV8mKK1v0eoBEhtWiNUfTjKD2nFVYAVBq79i8/enu 3flFx7DKZjPeEoB5VUm3iuo4Bw== X-Google-Smtp-Source: APXvYqz+VYXFM+4XZeOXyIhjD49lx+yExSB7FEN4yZZIGxqakwdynspTKJ2Yyypuipq9hBmIxa+3Ig== X-Received: by 2002:a1c:dfd6:: with SMTP id w205mr1621610wmg.151.1582674405950; Tue, 25 Feb 2020 15:46:45 -0800 (PST) Received: from linaro.org ([2a00:23c5:6815:3901:186c:5f6c:221d:5ce]) by smtp.gmail.com with ESMTPSA id t133sm356278wmf.31.2020.02.25.15.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2020 15:46:45 -0800 (PST) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, coresight@lists.linaro.org, linux-doc@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, mathieu.poirier@linaro.org, suzuki.poulose@arm.com, robh+dt@kernel.org, maxime@cerno.tech, liviu.dudau@arm.com, sudeep.holla@arm.com, lorenzo.pieralisi@arm.com, agross@kernel.org, corbet@lwn.net, Mike Leach Subject: [PATCH v10 10/15] dt-bindings: qcom: Add CTI options for qcom msm8916 Date: Tue, 25 Feb 2020 23:46:06 +0000 Message-Id: <20200225234611.11067-11-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200225234611.11067-1-mike.leach@linaro.org> References: <20200225234611.11067-1-mike.leach@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Adds system and CPU bound CTI definitions for Qualcom msm8916 platform (Dragonboard DB410C). System CTIs 2-11 are omitted as no information available at present. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier Acked-by: Suzuki K Poulose --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 85 +++++++++++++++++++++++++-- 1 file changed, 81 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 9f31064f2374..d13b5fb5c4d6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -1409,7 +1410,7 @@ cpu = <&CPU3>; }; - etm@85c000 { + etm0: etm@85c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85c000 0x1000>; @@ -1427,7 +1428,7 @@ }; }; - etm@85d000 { + etm1: etm@85d000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85d000 0x1000>; @@ -1445,7 +1446,7 @@ }; }; - etm@85e000 { + etm2: etm@85e000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85e000 0x1000>; @@ -1463,7 +1464,7 @@ }; }; - etm@85f000 { + etm3: etm@85f000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85f000 0x1000>; @@ -1481,6 +1482,82 @@ }; }; + /* System CTIs */ + /* CTI 0 - TMC connections */ + cti@810000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x810000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + /* CTI 1 - TPIU connections */ + cti@811000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x811000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + /* CTIs 2-11 - no information - not instantiated */ + + /* Core CTIs; CTIs 12-15 */ + /* CTI - CPU-0 */ + cti@858000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x858000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU0>; + arm,cs-dev-assoc = <&etm0>; + + }; + + /* CTI - CPU-1 */ + cti@859000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x859000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + arm,cs-dev-assoc = <&etm1>; + }; + + /* CTI - CPU-2 */ + cti@85a000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x85a000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU2>; + arm,cs-dev-assoc = <&etm2>; + }; + + /* CTI - CPU-3 */ + cti@85b000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x85b000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU3>; + arm,cs-dev-assoc = <&etm3>; + }; + + venus: video-codec@1d00000 { compatible = "qcom,msm8916-venus"; reg = <0x01d00000 0xff000>;