| Message ID | 20200407164915.v3.2.Iaddc29b72772e6ea381238a0ee85b82d3903e5f2@changeid (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | drivers: qcom: rpmh-rsc: Cleanup / add lots of comments | expand |
Hi, Reviewed-by: Maulik Shah <mkshah@codeaurora.org> Thanks, Maulik On 4/8/2020 5:20 AM, Douglas Anderson wrote: > Perhaps it's just me, it took a really long time to understand what > the register layout of rpmh-rsc was just from the #defines. Let's add > a bunch of comments describing which blocks are part of other blocks. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > --- > > Changes in v3: > - Extra blank line removed (Maulik). > - IRQ registers aren't in TCS0 (Maulik). > - One space after a period now (Maulik). > - Plural of TCS fixed to TCSes following Maulik's example. > - Rebased atop v16 ('Invoke rpmh_flush...') series. > > Changes in v2: > - Now prose in comments instead of struct definitions. > - Pretty ASCII art from Stephen. > > drivers/soc/qcom/rpmh-rsc.c | 79 ++++++++++++++++++++++++++++++++++--- > 1 file changed, 74 insertions(+), 5 deletions(-) > > diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c > index 7d9e2c2f0e27..46455b1d93f1 100644 > --- a/drivers/soc/qcom/rpmh-rsc.c > +++ b/drivers/soc/qcom/rpmh-rsc.c > @@ -43,14 +43,29 @@ > #define DRV_NCPT_MASK 0x1F > #define DRV_NCPT_SHIFT 27 > > -/* Register offsets */ > +/* Offsets for common TCS Registers, one bit per TCS */ > #define RSC_DRV_IRQ_ENABLE 0x00 > #define RSC_DRV_IRQ_STATUS 0x04 > -#define RSC_DRV_IRQ_CLEAR 0x08 > -#define RSC_DRV_CMD_WAIT_FOR_CMPL 0x10 > +#define RSC_DRV_IRQ_CLEAR 0x08 /* w/o; write 1 to clear */ > + > +/* > + * Offsets for per TCS Registers. > + * > + * TCSes start at 0x10 from tcs_base and are stored one after another. > + * Multiply tcs_id by RSC_DRV_TCS_OFFSET to find a given TCS and add one > + * of the below to find a register. > + */ > +#define RSC_DRV_CMD_WAIT_FOR_CMPL 0x10 /* 1 bit per command */ > #define RSC_DRV_CONTROL 0x14 > -#define RSC_DRV_STATUS 0x18 > -#define RSC_DRV_CMD_ENABLE 0x1C > +#define RSC_DRV_STATUS 0x18 /* zero if tcs is busy */ > +#define RSC_DRV_CMD_ENABLE 0x1C /* 1 bit per command */ > + > +/* > + * Offsets for per command in a TCS. > + * > + * Commands (up to 16) start at 0x30 in a TCS; multiply command index > + * by RSC_DRV_CMD_OFFSET and add one of the below to find a register. > + */ > #define RSC_DRV_CMD_MSGID 0x30 > #define RSC_DRV_CMD_ADDR 0x34 > #define RSC_DRV_CMD_DATA 0x38 > @@ -67,6 +82,60 @@ > #define CMD_STATUS_ISSUED BIT(8) > #define CMD_STATUS_COMPL BIT(16) > > +/* > + * Here's a high level overview of how all the registers in RPMH work > + * together: > + * > + * - The main rpmh-rsc address is the base of a register space that can > + * be used to find overall configuration of the hardware > + * (DRV_PRNT_CHLD_CONFIG). Also found within the rpmh-rsc register > + * space are all the TCS blocks. The offset of the TCS blocks is > + * specified in the device tree by "qcom,tcs-offset" and used to > + * compute tcs_base. > + * - TCS blocks come one after another. Type, count, and order are > + * specified by the device tree as "qcom,tcs-config". > + * - Each TCS block has some registers, then space for up to 16 commands. > + * Note that though address space is reserved for 16 commands, fewer > + * might be present. See ncpt (num cmds per TCS). > + * > + * Here's a picture: > + * > + * +---------------------------------------------------+ > + * |RSC | > + * | ctrl | > + * | | > + * | Drvs: | > + * | +-----------------------------------------------+ | > + * | |DRV0 | | > + * | | ctrl/config | | > + * | | IRQ | | > + * | | | | > + * | | TCSes: | | > + * | | +------------------------------------------+ | | > + * | | |TCS0 | | | | | | | | | | | | | | | > + * | | | ctrl | 0| 1| 2| 3| 4| 5| .| .| .| .|14|15| | | > + * | | | | | | | | | | | | | | | | | | > + * | | +------------------------------------------+ | | > + * | | +------------------------------------------+ | | > + * | | |TCS1 | | | | | | | | | | | | | | | > + * | | | ctrl | 0| 1| 2| 3| 4| 5| .| .| .| .|14|15| | | > + * | | | | | | | | | | | | | | | | | | > + * | | +------------------------------------------+ | | > + * | | +------------------------------------------+ | | > + * | | |TCS2 | | | | | | | | | | | | | | | > + * | | | ctrl | 0| 1| 2| 3| 4| 5| .| .| .| .|14|15| | | > + * | | | | | | | | | | | | | | | | | | > + * | | +------------------------------------------+ | | > + * | | ...... | | > + * | +-----------------------------------------------+ | > + * | +-----------------------------------------------+ | > + * | |DRV1 | | > + * | | (same as DRV0) | | > + * | +-----------------------------------------------+ | > + * | ...... | > + * +---------------------------------------------------+ > + */ > + > static u32 read_tcs_cmd(struct rsc_drv *drv, int reg, int tcs_id, int cmd_id) > { > return readl_relaxed(drv->tcs_base + RSC_DRV_TCS_OFFSET * tcs_id + reg +
diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index 7d9e2c2f0e27..46455b1d93f1 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -43,14 +43,29 @@ #define DRV_NCPT_MASK 0x1F #define DRV_NCPT_SHIFT 27 -/* Register offsets */ +/* Offsets for common TCS Registers, one bit per TCS */ #define RSC_DRV_IRQ_ENABLE 0x00 #define RSC_DRV_IRQ_STATUS 0x04 -#define RSC_DRV_IRQ_CLEAR 0x08 -#define RSC_DRV_CMD_WAIT_FOR_CMPL 0x10 +#define RSC_DRV_IRQ_CLEAR 0x08 /* w/o; write 1 to clear */ + +/* + * Offsets for per TCS Registers. + * + * TCSes start at 0x10 from tcs_base and are stored one after another. + * Multiply tcs_id by RSC_DRV_TCS_OFFSET to find a given TCS and add one + * of the below to find a register. + */ +#define RSC_DRV_CMD_WAIT_FOR_CMPL 0x10 /* 1 bit per command */ #define RSC_DRV_CONTROL 0x14 -#define RSC_DRV_STATUS 0x18 -#define RSC_DRV_CMD_ENABLE 0x1C +#define RSC_DRV_STATUS 0x18 /* zero if tcs is busy */ +#define RSC_DRV_CMD_ENABLE 0x1C /* 1 bit per command */ + +/* + * Offsets for per command in a TCS. + * + * Commands (up to 16) start at 0x30 in a TCS; multiply command index + * by RSC_DRV_CMD_OFFSET and add one of the below to find a register. + */ #define RSC_DRV_CMD_MSGID 0x30 #define RSC_DRV_CMD_ADDR 0x34 #define RSC_DRV_CMD_DATA 0x38 @@ -67,6 +82,60 @@ #define CMD_STATUS_ISSUED BIT(8) #define CMD_STATUS_COMPL BIT(16) +/* + * Here's a high level overview of how all the registers in RPMH work + * together: + * + * - The main rpmh-rsc address is the base of a register space that can + * be used to find overall configuration of the hardware + * (DRV_PRNT_CHLD_CONFIG). Also found within the rpmh-rsc register + * space are all the TCS blocks. The offset of the TCS blocks is + * specified in the device tree by "qcom,tcs-offset" and used to + * compute tcs_base. + * - TCS blocks come one after another. Type, count, and order are + * specified by the device tree as "qcom,tcs-config". + * - Each TCS block has some registers, then space for up to 16 commands. + * Note that though address space is reserved for 16 commands, fewer + * might be present. See ncpt (num cmds per TCS). + * + * Here's a picture: + * + * +---------------------------------------------------+ + * |RSC | + * | ctrl | + * | | + * | Drvs: | + * | +-----------------------------------------------+ | + * | |DRV0 | | + * | | ctrl/config | | + * | | IRQ | | + * | | | | + * | | TCSes: | | + * | | +------------------------------------------+ | | + * | | |TCS0 | | | | | | | | | | | | | | | + * | | | ctrl | 0| 1| 2| 3| 4| 5| .| .| .| .|14|15| | | + * | | | | | | | | | | | | | | | | | | + * | | +------------------------------------------+ | | + * | | +------------------------------------------+ | | + * | | |TCS1 | | | | | | | | | | | | | | | + * | | | ctrl | 0| 1| 2| 3| 4| 5| .| .| .| .|14|15| | | + * | | | | | | | | | | | | | | | | | | + * | | +------------------------------------------+ | | + * | | +------------------------------------------+ | | + * | | |TCS2 | | | | | | | | | | | | | | | + * | | | ctrl | 0| 1| 2| 3| 4| 5| .| .| .| .|14|15| | | + * | | | | | | | | | | | | | | | | | | + * | | +------------------------------------------+ | | + * | | ...... | | + * | +-----------------------------------------------+ | + * | +-----------------------------------------------+ | + * | |DRV1 | | + * | | (same as DRV0) | | + * | +-----------------------------------------------+ | + * | ...... | + * +---------------------------------------------------+ + */ + static u32 read_tcs_cmd(struct rsc_drv *drv, int reg, int tcs_id, int cmd_id) { return readl_relaxed(drv->tcs_base + RSC_DRV_TCS_OFFSET * tcs_id + reg +
Perhaps it's just me, it took a really long time to understand what the register layout of rpmh-rsc was just from the #defines. Let's add a bunch of comments describing which blocks are part of other blocks. Signed-off-by: Douglas Anderson <dianders@chromium.org> --- Changes in v3: - Extra blank line removed (Maulik). - IRQ registers aren't in TCS0 (Maulik). - One space after a period now (Maulik). - Plural of TCS fixed to TCSes following Maulik's example. - Rebased atop v16 ('Invoke rpmh_flush...') series. Changes in v2: - Now prose in comments instead of struct definitions. - Pretty ASCII art from Stephen. drivers/soc/qcom/rpmh-rsc.c | 79 ++++++++++++++++++++++++++++++++++--- 1 file changed, 74 insertions(+), 5 deletions(-)