From patchwork Thu Jul 9 13:52:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 11654423 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F3D73913 for ; Thu, 9 Jul 2020 13:54:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D5D25207DA for ; Thu, 9 Jul 2020 13:54:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=marek-ca.20150623.gappssmtp.com header.i=@marek-ca.20150623.gappssmtp.com header.b="hi8Dc18Z" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728173AbgGINyw (ORCPT ); Thu, 9 Jul 2020 09:54:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728170AbgGINyw (ORCPT ); Thu, 9 Jul 2020 09:54:52 -0400 Received: from mail-qv1-xf42.google.com (mail-qv1-xf42.google.com [IPv6:2607:f8b0:4864:20::f42]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C915FC08E876 for ; Thu, 9 Jul 2020 06:54:50 -0700 (PDT) Received: by mail-qv1-xf42.google.com with SMTP id t7so941488qvl.8 for ; Thu, 09 Jul 2020 06:54:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8FsLSSR0MxMIrn21H5ZMps5SE+xvS8TdF2kEFRPFarM=; b=hi8Dc18Z9I05d+21n6Ck++N2RHv0Wj8URmB2+nuntR7cPvkiAbl29uRrJnHDfJj2cm +KDSIHOMvcEOJN/MmCBlfazdirfjDcRGE3LF7XHhoCqzinZHSNtuQPwStUCFiBG3/XMm GIp3LyS1fzpB9Zw5C+yrCpSxCkUsMSe8/JESqvbSCI42FJKr/S/g4kYnm2liYS0x+bfl xHHMBtTo5Ha7zuhTSy4+L5Z3TKbmUCERaV6Ga2tf/YtHabe96q9cXSHeONfll5z2fmXG 7kjE7CRpEh2qze6e8E58bPUr0uK2itVYykvFN4tdh/l9vngm0Fva+BgIDVhAet6gqWsA D3Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8FsLSSR0MxMIrn21H5ZMps5SE+xvS8TdF2kEFRPFarM=; b=Zyc25+CxD24r4BS5raqWd63dFz7JJmEy0qPZfDZiaA4lp/nLCEDNkHVhV96W7ElJM3 MNEFuSNq00NR3c3Ub1sR1C3mbhwtZ3cBUyWyN0XfpKw3enR0uSCKyijSf8kwcETfOet2 uqCQNE72tzg4/Zww1sMjz95jVq4I6VpUYKIG+ZEAZLckT0WfwrMWSqVZh/Aj9x90XWzC eksGAJTyLf0Hmb3gy3PWdQIdhyyv4HxmUfpmacS1IktWmlQBoGjxvpB7RU0elglRuSqw 1btUTA64VymJUV25GpJhqGN0G8S4CLMlbzz9Et6tX046YvDTDoNLcbKYPCuA1rookoXU pPZw== X-Gm-Message-State: AOAM532hZldvqDLrS69iesmRfNaYMBvDXRNfAd00j5/UfvhqTbIL0kJq FFk5melvB4bdXoaSvX1PwPmePs8syQc= X-Google-Smtp-Source: ABdhPJyUJaN8Tn5qtd/PkJVlPM+c9a2L7KjV+uRwH2SXs4MPmMoy8PcUUBJHHO+Lhrdg7Iv3cqP8AA== X-Received: by 2002:a0c:bc14:: with SMTP id j20mr36276903qvg.40.1594302889877; Thu, 09 Jul 2020 06:54:49 -0700 (PDT) Received: from localhost.localdomain ([147.253.86.153]) by smtp.gmail.com with ESMTPSA id 130sm3632735qkn.82.2020.07.09.06.54.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jul 2020 06:54:49 -0700 (PDT) From: Jonathan Marek To: linux-arm-msm@vger.kernel.org Cc: Andy Gross , Bjorn Andersson , Rob Herring , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 14/14] arm64: dts: qcom: add sm8250 GPU nodes Date: Thu, 9 Jul 2020 09:52:45 -0400 Message-Id: <20200709135251.643-15-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20200709135251.643-1-jonathan@marek.ca> References: <20200709135251.643-1-jonathan@marek.ca> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This brings up the GPU. Tested on HDK865 by running vulkan CTS. Signed-off-by: Jonathan Marek --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 143 +++++++++++++++++++++++++++ 1 file changed, 143 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 3564f233064c..636e2196138c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -1131,6 +1132,148 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; + gpu: gpu@3d00000 { + /* + * note: the amd,imageon compatible makes it possible + * to use the drm/msm driver without the display node, + * make sure to remove it when display node is added + */ + compatible = "qcom,adreno-650.2", + "qcom,adreno", + "amd,imageon"; + #stream-id-cells = <16>; + + reg = <0 0x3d00000 0 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x401>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + zap-shader { + memory-region = <&gpu_mem>; + }; + + /* note: downstream checks gpu binning for 670 Mhz */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-670000000 { + opp-hz = /bits/ 64 <670000000>; + opp-level = ; + }; + + opp-587000000 { + opp-hz = /bits/ 64 <587000000>; + opp-level = ; + }; + + opp-525000000 { + opp-hz = /bits/ 64 <525000000>; + opp-level = ; + }; + + opp-490000000 { + opp-hz = /bits/ 64 <490000000>; + opp-level = ; + }; + + opp-441600000 { + opp-hz = /bits/ 64 <441600000>; + opp-level = ; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-level = ; + }; + + opp-305000000 { + opp-hz = /bits/ 64 <305000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; + + reg = <0 0x3d6a000 0 0x30000>, + <0 0x3de0000 0 0x10000>, + <0 0xb290000 0 0x10000>, + <0 0xb490000 0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + + iommus = <&adreno_smmu 5 0x400>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm8250-gpucc"; + reg = <0 0x3d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; + reg = <0 0x3da0000 0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "ahb", "bus", "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm8250-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy";