Message ID | 20200817081138.6755-1-saiprakash.ranjan@codeaurora.org (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | soc: qcom: llcc: Support chipsets that can write to llcc registers | expand |
Hi Sai, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on linux/master] [also build test WARNING on linus/master v5.9-rc1 next-20200817] [cannot apply to agross-msm/qcom/for-next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Sai-Prakash-Ranjan/soc-qcom-llcc-Support-chipsets-that-can-write-to-llcc-registers/20200817-161342 base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git bcf876870b95592b52519ed4aafcf9d95999bc9c config: mips-randconfig-r006-20200817 (attached as .config) compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project de71b46a519db014ce906a39f8a0e1b235ef1568) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install mips cross compiling tool for clang build # apt-get install binutils-mips-linux-gnu # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=mips If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All warnings (new ones prefixed by >>): drivers/soc/qcom/llcc-qcom.c:343:28: warning: unused variable 'np' [-Wunused-variable] const struct device_node *np = dev_of_node(&pdev->dev); ^ >> drivers/soc/qcom/llcc-qcom.c:324:34: warning: unused variable 'qcom_llcc_configure_of_match' [-Wunused-const-variable] static const struct of_device_id qcom_llcc_configure_of_match[] = { ^ 2 warnings generated. # https://github.com/0day-ci/linux/commit/69ff7ebbde628483bfe9eacd588984bdae4d6121 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Sai-Prakash-Ranjan/soc-qcom-llcc-Support-chipsets-that-can-write-to-llcc-registers/20200817-161342 git checkout 69ff7ebbde628483bfe9eacd588984bdae4d6121 vim +/qcom_llcc_configure_of_match +324 drivers/soc/qcom/llcc-qcom.c 323 > 324 static const struct of_device_id qcom_llcc_configure_of_match[] = { 325 { .compatible = "qcom,sc7180-llcc" }, 326 { } 327 }; 328 329 static int qcom_llcc_cfg_program(struct platform_device *pdev) 330 { 331 int i; 332 u32 attr1_cfg; 333 u32 attr0_cfg; 334 u32 attr1_val; 335 u32 attr0_val; 336 u32 max_cap_cacheline; 337 u32 sz; 338 u32 disable_cap_alloc = 0, retain_pc = 0; 339 int ret = 0; 340 const struct llcc_slice_config *llcc_table; 341 struct llcc_slice_desc desc; 342 const struct of_device_id *llcc_configure; > 343 const struct device_node *np = dev_of_node(&pdev->dev); 344 345 sz = drv_data->cfg_size; 346 llcc_table = drv_data->cfg; 347 348 llcc_configure = of_match_node(qcom_llcc_configure_of_match, np); 349 350 for (i = 0; i < sz; i++) { 351 attr1_cfg = LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id); 352 attr0_cfg = LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id); 353 354 attr1_val = llcc_table[i].cache_mode; 355 attr1_val |= llcc_table[i].probe_target_ways << 356 ATTR1_PROBE_TARGET_WAYS_SHIFT; 357 attr1_val |= llcc_table[i].fixed_size << 358 ATTR1_FIXED_SIZE_SHIFT; 359 attr1_val |= llcc_table[i].priority << 360 ATTR1_PRIORITY_SHIFT; 361 362 max_cap_cacheline = MAX_CAP_TO_BYTES(llcc_table[i].max_cap); 363 364 /* LLCC instances can vary for each target. 365 * The SW writes to broadcast register which gets propagated 366 * to each llcc instace (llcc0,.. llccN). 367 * Since the size of the memory is divided equally amongst the 368 * llcc instances, we need to configure the max cap accordingly. 369 */ 370 max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; 371 max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT; 372 attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; 373 374 attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK; 375 attr0_val |= llcc_table[i].bonus_ways << ATTR0_BONUS_WAYS_SHIFT; 376 377 ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, 378 attr1_val); 379 if (ret) 380 return ret; 381 ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, 382 attr0_val); 383 if (ret) 384 return ret; 385 386 if (llcc_configure) { 387 disable_cap_alloc |= llcc_table[i].dis_cap_alloc << llcc_table[i].slice_id; 388 ret = regmap_write(drv_data->bcast_regmap, 389 LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc); 390 if (ret) 391 return ret; 392 393 retain_pc |= llcc_table[i].retain_on_pc << llcc_table[i].slice_id; 394 ret = regmap_write(drv_data->bcast_regmap, 395 LLCC_TRP_PCB_ACT, retain_pc); 396 if (ret) 397 return ret; 398 } 399 400 if (llcc_table[i].activate_on_init) { 401 desc.slice_id = llcc_table[i].slice_id; 402 ret = llcc_slice_activate(&desc); 403 } 404 } 405 return ret; 406 } 407 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
On 2020-08-17 18:13, kernel test robot wrote: > Hi Sai, > > Thank you for the patch! Perhaps something to improve: > > [auto build test WARNING on linux/master] > [also build test WARNING on linus/master v5.9-rc1 next-20200817] > [cannot apply to agross-msm/qcom/for-next] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch] > > url: > https://github.com/0day-ci/linux/commits/Sai-Prakash-Ranjan/soc-qcom-llcc-Support-chipsets-that-can-write-to-llcc-registers/20200817-161342 > base: > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git > bcf876870b95592b52519ed4aafcf9d95999bc9c > config: mips-randconfig-r006-20200817 (attached as .config) > compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project > de71b46a519db014ce906a39f8a0e1b235ef1568) > reproduce (this is a W=1 build): > wget > https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross > -O ~/bin/make.cross > chmod +x ~/bin/make.cross > # install mips cross compiling tool for clang build > # apt-get install binutils-mips-linux-gnu > # save the attached .config to linux build tree > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross > ARCH=mips > > If you fix the issue, kindly add following tag as appropriate > Reported-by: kernel test robot <lkp@intel.com> > > All warnings (new ones prefixed by >>): > > drivers/soc/qcom/llcc-qcom.c:343:28: warning: unused variable 'np' > [-Wunused-variable] > const struct device_node *np = dev_of_node(&pdev->dev); > ^ >>> drivers/soc/qcom/llcc-qcom.c:324:34: warning: unused variable >>> 'qcom_llcc_configure_of_match' [-Wunused-const-variable] > static const struct of_device_id qcom_llcc_configure_of_match[] = { > ^ > 2 warnings generated. > Ok, W=1 build and CONFIG_OF=n, so I need __maybe_unused for qcom_llcc_configure_of_match. Will add and send v2. Thanks, Sai
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 429b5a60a1ba..20619d15ecba 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -45,6 +45,9 @@ #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) +#define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21F00 +#define LLCC_TRP_PCB_ACT 0x21F04 + #define BANK_OFFSET_STRIDE 0x80000 /** @@ -318,6 +321,11 @@ size_t llcc_get_slice_size(struct llcc_slice_desc *desc) } EXPORT_SYMBOL_GPL(llcc_get_slice_size); +static const struct of_device_id qcom_llcc_configure_of_match[] = { + { .compatible = "qcom,sc7180-llcc" }, + { } +}; + static int qcom_llcc_cfg_program(struct platform_device *pdev) { int i; @@ -327,13 +335,18 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev) u32 attr0_val; u32 max_cap_cacheline; u32 sz; + u32 disable_cap_alloc = 0, retain_pc = 0; int ret = 0; const struct llcc_slice_config *llcc_table; struct llcc_slice_desc desc; + const struct of_device_id *llcc_configure; + const struct device_node *np = dev_of_node(&pdev->dev); sz = drv_data->cfg_size; llcc_table = drv_data->cfg; + llcc_configure = of_match_node(qcom_llcc_configure_of_match, np); + for (i = 0; i < sz; i++) { attr1_cfg = LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id); attr0_cfg = LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id); @@ -369,6 +382,21 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev) attr0_val); if (ret) return ret; + + if (llcc_configure) { + disable_cap_alloc |= llcc_table[i].dis_cap_alloc << llcc_table[i].slice_id; + ret = regmap_write(drv_data->bcast_regmap, + LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc); + if (ret) + return ret; + + retain_pc |= llcc_table[i].retain_on_pc << llcc_table[i].slice_id; + ret = regmap_write(drv_data->bcast_regmap, + LLCC_TRP_PCB_ACT, retain_pc); + if (ret) + return ret; + } + if (llcc_table[i].activate_on_init) { desc.slice_id = llcc_table[i].slice_id; ret = llcc_slice_activate(&desc);