| Message ID | 20200902183852.14510-3-jonathan@marek.ca (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | SM8150 and SM8250 dispcc drivers | expand |
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2884577dcb77..8184d6204b33 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4139,8 +4139,8 @@ dispcc: clock-controller@af00000 { "dsi0_phy_pll_out_dsiclk", "dsi1_phy_pll_out_byteclk", "dsi1_phy_pll_out_dsiclk", - "dp_link_clk_divsel_ten", - "dp_vco_divided_clk_src_mux"; + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;
This makes it easier to combine dt bindings for sdm845/sc7180 dispcc. Note: nothing upstream provides these clocks and the sdm845 dispcc driver hasn't switched to using .fw_name for these clocks (these properties are ignored), so changing this shouldn't be a problem. Signed-off-by: Jonathan Marek <jonathan@marek.ca> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)