| Message ID | 20200911153412.21672-2-jonathan@marek.ca (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | SM8150 and SM8250 dispcc drivers | expand |
On Fri, 11 Sep 2020 11:34:01 -0400, Jonathan Marek wrote: > This makes it easier to combine dt bindings for sdm845/sc7180 dispcc. > > Note: nothing upstream provides these clocks and the sdm845 dispcc driver > hasn't switched to using .fw_name for these clocks (these properties are > ignored), so changing this shouldn't be a problem. > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > --- > .../devicetree/bindings/clock/qcom,sdm845-dispcc.yaml | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml index 4a3be733d042..ead44705333b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml @@ -43,8 +43,8 @@ properties: - const: dsi0_phy_pll_out_dsiclk - const: dsi1_phy_pll_out_byteclk - const: dsi1_phy_pll_out_dsiclk - - const: dp_link_clk_divsel_ten - - const: dp_vco_divided_clk_src_mux + - const: dp_phy_pll_link_clk + - const: dp_phy_pll_vco_div_clk '#clock-cells': const: 1 @@ -92,8 +92,8 @@ examples: "dsi0_phy_pll_out_dsiclk", "dsi1_phy_pll_out_byteclk", "dsi1_phy_pll_out_dsiclk", - "dp_link_clk_divsel_ten", - "dp_vco_divided_clk_src_mux"; + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;
This makes it easier to combine dt bindings for sdm845/sc7180 dispcc. Note: nothing upstream provides these clocks and the sdm845 dispcc driver hasn't switched to using .fw_name for these clocks (these properties are ignored), so changing this shouldn't be a problem. Signed-off-by: Jonathan Marek <jonathan@marek.ca> --- .../devicetree/bindings/clock/qcom,sdm845-dispcc.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)