From patchwork Tue Sep 22 10:16:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 11792073 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5847E92C for ; Tue, 22 Sep 2020 10:17:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 292DF2395C for ; Tue, 22 Sep 2020 10:17:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sartura-hr.20150623.gappssmtp.com header.i=@sartura-hr.20150623.gappssmtp.com header.b="qfjrHGnP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726419AbgIVKQ7 (ORCPT ); Tue, 22 Sep 2020 06:16:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726607AbgIVKQp (ORCPT ); Tue, 22 Sep 2020 06:16:45 -0400 Received: from mail-ej1-x644.google.com (mail-ej1-x644.google.com [IPv6:2a00:1450:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F17ECC0613D1 for ; Tue, 22 Sep 2020 03:16:44 -0700 (PDT) Received: by mail-ej1-x644.google.com with SMTP id gx22so12984693ejb.5 for ; Tue, 22 Sep 2020 03:16:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura-hr.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LGX6bMTHeK9dl0OlUYi3pEreR5jusQDI4rgzHH0PXrY=; b=qfjrHGnP/i79awJU19BgoDoHfklS2j55O1X+ktD7J5cDQhvoK5Jp5IZEIydAsFYslR p/Oo3FzkyGG6u5XGywldonY1dzL6TtL8xD7QddOCWB69cWIbHqydL5W3gsz04QhzrmM+ JZFHSVww2z/v7FeYCSqhrsD2dz17oQCk6Lidi/EXi5LW7R+B86HwlpnYU7cJdlrG3qZV v+qYmHWwcvh3khws70/JcX7bjhNtsIkO2dNxvpflTbP2VGwnzWgygoPZt6/XnBg2HD/7 VvDco0y8FKewzgV+I/II+EGPY3JXOJKsBrdvr6JnyiLmHOLAqXm8mZOYHGIpv2yD8TDs 5w3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LGX6bMTHeK9dl0OlUYi3pEreR5jusQDI4rgzHH0PXrY=; b=pIHyQXt/kv6c+5rAD0K8WHKxP11teXqxdlmoPKLQZIXQ5OHmuvpsQGkgqb0zf57T1P pGx5+LVz1ZB2nTWViiBxPWxdUXuZAXLdxh/IVo2NnmvkESFA7OiqwDklMZWY8jB3K/jR U0lmhwN52tcQ0vR+k2gfrhPPMqxnY6IK00olzv+jL/L29GfTXpqJPhahFZhB/MIltfH5 flUVBDQlM9JQRgaIXORkvcz4pn1l8fpzxP+PluDtST8Bz5RYzlqmmtFHzz2bGqiMhllm o7u//rYEQlbRwJMitnWMpaP93ekoX6GCz3PswggKUX/D4Cgrloda476S0qRMbSRDzTtM aLtg== X-Gm-Message-State: AOAM533njMA9d+1oHP3nEgva1CswIX721iroGxa9pqgEh48D2jk/X0ka 1sq+y3PwHWfHV4DDtX0lf/oC7A== X-Google-Smtp-Source: ABdhPJzF5DGwi8aLAsaKOamx3h90UQXbre99VtUmtnWWes3AKtPAunD6dDsPEdgcfn6R3rd/AyRJTw== X-Received: by 2002:a17:906:cec9:: with SMTP id si9mr3955841ejb.351.1600769803625; Tue, 22 Sep 2020 03:16:43 -0700 (PDT) Received: from localhost.localdomain ([88.207.4.22]) by smtp.googlemail.com with ESMTPSA id p3sm10595368edp.28.2020.09.22.03.16.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2020 03:16:43 -0700 (PDT) From: Robert Marko To: andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, kuba@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Robert Marko , Luka Perkov Subject: [PATCH v5 2/2] net: mdio-ipq4019: add Clause 45 support Date: Tue, 22 Sep 2020 12:16:32 +0200 Message-Id: <20200922101632.54896-3-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200922101632.54896-1-robert.marko@sartura.hr> References: <20200922101632.54896-1-robert.marko@sartura.hr> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org While up-streaming the IPQ4019 driver it was thought that the controller had no Clause 45 support, but it actually does and its activated by writing a bit to the mode register. So lets add it as newer SoC-s use the same controller and Clause 45 compliant PHY-s. Signed-off-by: Robert Marko Cc: Luka Perkov Reviewed-by: Andrew Lunn --- Changes since v4: * Rebase onto net-next.git Changes since v3: * Rename MDIO_MODE_BIT to MDIO_MODE_C45 Changes since v2: * Fix missed reverse christmas tree Changes since v1: * Maintain reverse christmas tree drivers/net/mdio/mdio-ipq4019.c | 103 +++++++++++++++++++++++++++----- 1 file changed, 89 insertions(+), 14 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 64b169e5a699..25c25ea6da66 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -12,6 +12,7 @@ #include #include +#define MDIO_MODE_REG 0x40 #define MDIO_ADDR_REG 0x44 #define MDIO_DATA_WRITE_REG 0x48 #define MDIO_DATA_READ_REG 0x4c @@ -20,6 +21,12 @@ #define MDIO_CMD_ACCESS_START BIT(8) #define MDIO_CMD_ACCESS_CODE_READ 0 #define MDIO_CMD_ACCESS_CODE_WRITE 1 +#define MDIO_CMD_ACCESS_CODE_C45_ADDR 0 +#define MDIO_CMD_ACCESS_CODE_C45_WRITE 1 +#define MDIO_CMD_ACCESS_CODE_C45_READ 2 + +/* 0 = Clause 22, 1 = Clause 45 */ +#define MDIO_MODE_C45 BIT(8) #define IPQ4019_MDIO_TIMEOUT 10000 #define IPQ4019_MDIO_SLEEP 10 @@ -41,19 +48,44 @@ static int ipq4019_mdio_wait_busy(struct mii_bus *bus) static int ipq4019_mdio_read(struct mii_bus *bus, int mii_id, int regnum) { struct ipq4019_mdio_data *priv = bus->priv; + unsigned int data; unsigned int cmd; - /* Reject clause 45 */ - if (regnum & MII_ADDR_C45) - return -EOPNOTSUPP; - if (ipq4019_mdio_wait_busy(bus)) return -ETIMEDOUT; - /* issue the phy address and reg */ - writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); + /* Clause 45 support */ + if (regnum & MII_ADDR_C45) { + unsigned int mmd = (regnum >> 16) & 0x1F; + unsigned int reg = regnum & 0xFFFF; + + /* Enter Clause 45 mode */ + data = readl(priv->membase + MDIO_MODE_REG); + + data |= MDIO_MODE_C45; + + writel(data, priv->membase + MDIO_MODE_REG); + + /* issue the phy address and mmd */ + writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); + + /* issue reg */ + writel(reg, priv->membase + MDIO_DATA_WRITE_REG); + + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_ADDR; + } else { + /* Enter Clause 22 mode */ + data = readl(priv->membase + MDIO_MODE_REG); - cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ; + data &= ~MDIO_MODE_C45; + + writel(data, priv->membase + MDIO_MODE_REG); + + /* issue the phy address and reg */ + writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); + + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ; + } /* issue read command */ writel(cmd, priv->membase + MDIO_CMD_REG); @@ -62,6 +94,15 @@ static int ipq4019_mdio_read(struct mii_bus *bus, int mii_id, int regnum) if (ipq4019_mdio_wait_busy(bus)) return -ETIMEDOUT; + if (regnum & MII_ADDR_C45) { + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_READ; + + writel(cmd, priv->membase + MDIO_CMD_REG); + + if (ipq4019_mdio_wait_busy(bus)) + return -ETIMEDOUT; + } + /* Read and return data */ return readl(priv->membase + MDIO_DATA_READ_REG); } @@ -70,23 +111,57 @@ static int ipq4019_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value) { struct ipq4019_mdio_data *priv = bus->priv; + unsigned int data; unsigned int cmd; - /* Reject clause 45 */ - if (regnum & MII_ADDR_C45) - return -EOPNOTSUPP; - if (ipq4019_mdio_wait_busy(bus)) return -ETIMEDOUT; - /* issue the phy address and reg */ - writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); + /* Clause 45 support */ + if (regnum & MII_ADDR_C45) { + unsigned int mmd = (regnum >> 16) & 0x1F; + unsigned int reg = regnum & 0xFFFF; + + /* Enter Clause 45 mode */ + data = readl(priv->membase + MDIO_MODE_REG); + + data |= MDIO_MODE_C45; + + writel(data, priv->membase + MDIO_MODE_REG); + + /* issue the phy address and mmd */ + writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); + + /* issue reg */ + writel(reg, priv->membase + MDIO_DATA_WRITE_REG); + + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_ADDR; + + writel(cmd, priv->membase + MDIO_CMD_REG); + + if (ipq4019_mdio_wait_busy(bus)) + return -ETIMEDOUT; + } else { + /* Enter Clause 22 mode */ + data = readl(priv->membase + MDIO_MODE_REG); + + data &= ~MDIO_MODE_C45; + + writel(data, priv->membase + MDIO_MODE_REG); + + /* issue the phy address and reg */ + writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); + } /* issue write data */ writel(value, priv->membase + MDIO_DATA_WRITE_REG); - cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE; /* issue write command */ + if (regnum & MII_ADDR_C45) + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_WRITE; + else + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE; + writel(cmd, priv->membase + MDIO_CMD_REG); /* Wait write complete */