diff mbox series

[RFT] arm64: dts: sdm845: Add iommus property to qup

Message ID 20201020150301.3259814-1-bjorn.andersson@linaro.org
State Superseded
Headers show
Series [RFT] arm64: dts: sdm845: Add iommus property to qup | expand

Commit Message

Bjorn Andersson Oct. 20, 2020, 3:03 p.m. UTC
From: Stephen Boyd <swboyd@chromium.org>

The SMMU that sits in front of the QUP needs to be programmed properly
so that the i2c geni driver can allocate DMA descriptors. Failure to do
this leads to faults when using devices such as an i2c touchscreen where
the transaction is larger than 32 bytes and we use a DMA buffer.

arm-smmu 15000000.iommu: Unexpected global fault, this could be serious
arm-smmu 15000000.iommu:         GFSR 0x00000002, GFSYNR0 0x00000002, GFSYNR1 0x000006c0, GFSYNR2 0x00000000

Add the right SID and mask so this works.

Signed-off-by: Stephen Boyd <swboyd@chromium.org>
[bjorn: Define for second QUP as well]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++
 1 file changed, 2 insertions(+)

Comments

Vinod Koul Oct. 21, 2020, 6:50 a.m. UTC | #1
Hi Bjorn, Steve,

On 20-10-20, 08:03, Bjorn Andersson wrote:
> From: Stephen Boyd <swboyd@chromium.org>
> 
> The SMMU that sits in front of the QUP needs to be programmed properly
> so that the i2c geni driver can allocate DMA descriptors. Failure to do
> this leads to faults when using devices such as an i2c touchscreen where
> the transaction is larger than 32 bytes and we use a DMA buffer.

So I tried this and results in reboot for me when I use it in GSI
driver in RB3. I seem to already have the iommu properties [1] but values
are different

[1]: https://git.linaro.org/people/vinod.koul/kernel.git/commit/?h=topic/gsi3-db&id=385edef08d55432a40fc9a8ae1f49248d5417a92

> arm-smmu 15000000.iommu: Unexpected global fault, this could be serious
> arm-smmu 15000000.iommu:         GFSR 0x00000002, GFSYNR0 0x00000002, GFSYNR1 0x000006c0, GFSYNR2 0x00000000
> 
> Add the right SID and mask so this works.
> 
> Signed-off-by: Stephen Boyd <swboyd@chromium.org>
> [bjorn: Define for second QUP as well]
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 8eb5a31346d2..7d635bc919cb 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -811,6 +811,7 @@ qupv3_id_0: geniqup@8c0000 {
>  			clock-names = "m-ahb", "s-ahb";
>  			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
>  				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> +			iommus = <&apps_smmu 0x0 0x3>;
>  			#address-cells = <2>;
>  			#size-cells = <2>;
>  			ranges;
> @@ -1119,6 +1120,7 @@ qupv3_id_1: geniqup@ac0000 {
>  			clock-names = "m-ahb", "s-ahb";
>  			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
>  				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> +			iommus = <&apps_smmu 0x6c0 0x3>;
>  			#address-cells = <2>;
>  			#size-cells = <2>;
>  			ranges;
> -- 
> 2.28.0
Bjorn Andersson Oct. 21, 2020, 3:38 p.m. UTC | #2
On Wed 21 Oct 01:50 CDT 2020, Vinod Koul wrote:

> Hi Bjorn, Steve,
> 
> On 20-10-20, 08:03, Bjorn Andersson wrote:
> > From: Stephen Boyd <swboyd@chromium.org>
> > 
> > The SMMU that sits in front of the QUP needs to be programmed properly
> > so that the i2c geni driver can allocate DMA descriptors. Failure to do
> > this leads to faults when using devices such as an i2c touchscreen where
> > the transaction is larger than 32 bytes and we use a DMA buffer.
> 
> So I tried this and results in reboot for me when I use it in GSI
> driver in RB3. I seem to already have the iommu properties [1] but values
> are different
> 
> [1]: https://git.linaro.org/people/vinod.koul/kernel.git/commit/?h=topic/gsi3-db&id=385edef08d55432a40fc9a8ae1f49248d5417a92

Thanks for the testing, I was hoping to cover the two related streams in
one go - but in a discussion with Sai yesterday we concluded that it
would be better to just pinpoint the one stream that we know is relevant
for us. Hopefully this is the cause for the crash you're seeing as
well...

I will resend this in line with our discussion.

Thanks,
Bjorn

> 
> > arm-smmu 15000000.iommu: Unexpected global fault, this could be serious
> > arm-smmu 15000000.iommu:         GFSR 0x00000002, GFSYNR0 0x00000002, GFSYNR1 0x000006c0, GFSYNR2 0x00000000
> > 
> > Add the right SID and mask so this works.
> > 
> > Signed-off-by: Stephen Boyd <swboyd@chromium.org>
> > [bjorn: Define for second QUP as well]
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > ---
> >  arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > index 8eb5a31346d2..7d635bc919cb 100644
> > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > @@ -811,6 +811,7 @@ qupv3_id_0: geniqup@8c0000 {
> >  			clock-names = "m-ahb", "s-ahb";
> >  			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> >  				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> > +			iommus = <&apps_smmu 0x0 0x3>;
> >  			#address-cells = <2>;
> >  			#size-cells = <2>;
> >  			ranges;
> > @@ -1119,6 +1120,7 @@ qupv3_id_1: geniqup@ac0000 {
> >  			clock-names = "m-ahb", "s-ahb";
> >  			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> >  				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> > +			iommus = <&apps_smmu 0x6c0 0x3>;
> >  			#address-cells = <2>;
> >  			#size-cells = <2>;
> >  			ranges;
> > -- 
> > 2.28.0
> 
> -- 
> ~Vinod
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 8eb5a31346d2..7d635bc919cb 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -811,6 +811,7 @@  qupv3_id_0: geniqup@8c0000 {
 			clock-names = "m-ahb", "s-ahb";
 			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+			iommus = <&apps_smmu 0x0 0x3>;
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges;
@@ -1119,6 +1120,7 @@  qupv3_id_1: geniqup@ac0000 {
 			clock-names = "m-ahb", "s-ahb";
 			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+			iommus = <&apps_smmu 0x6c0 0x3>;
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges;