| Message ID | 20210106005038.4152731-1-bjorn.andersson@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | aded8c7c2b72f846a07a2c736b8e75bb8cf50a87 |
| Headers | show |
| Series | iommu/arm-smmu-qcom: Initialize SCTLR of the bypass context | expand |
On Tue, 5 Jan 2021 16:50:38 -0800, Bjorn Andersson wrote: > On SM8150 it's occasionally observed that the boot hangs in between the > writing of SMEs and context banks in arm_smmu_device_reset(). > > The problem seems to coincide with a display refresh happening after > updating the stream mapping, but before clearing - and there by > disabling translation - the context bank picked to emulate translation > bypass. > > [...] Applied to arm64 (for-next/iommu/fixes), thanks! [1/1] iommu/arm-smmu-qcom: Initialize SCTLR of the bypass context https://git.kernel.org/arm64/c/aded8c7c2b72 Cheers,
Hello: This patch was applied to qcom/linux.git (refs/heads/for-next): On Tue, 5 Jan 2021 16:50:38 -0800 you wrote: > On SM8150 it's occasionally observed that the boot hangs in between the > writing of SMEs and context banks in arm_smmu_device_reset(). > > The problem seems to coincide with a display refresh happening after > updating the stream mapping, but before clearing - and there by > disabling translation - the context bank picked to emulate translation > bypass. > > [...] Here is the summary with links: - iommu/arm-smmu-qcom: Initialize SCTLR of the bypass context https://git.kernel.org/qcom/c/aded8c7c2b72 You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 5dff7ffbef11..1b83d140742f 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -196,6 +196,8 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) set_bit(qsmmu->bypass_cbndx, smmu->context_map); + arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); + reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS); arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg); }
On SM8150 it's occasionally observed that the boot hangs in between the writing of SMEs and context banks in arm_smmu_device_reset(). The problem seems to coincide with a display refresh happening after updating the stream mapping, but before clearing - and there by disabling translation - the context bank picked to emulate translation bypass. Resolve this by explicitly disabling the bypass context already in cfg_probe. Fixes: f9081b8ff593 ("iommu/arm-smmu-qcom: Implement S2CR quirk") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++ 1 file changed, 2 insertions(+)